Principal Design Verification Engineer, HBM

Job Title

Principal Design Verification Engineer, HBM

Role Summary

Lead verification for HBM and DRAM IP, subsystems, and full-chip designs to ensure functional correctness, performance, power efficiency, and delivery of production-quality silicon. Serve as a technical lead across design, architecture, and system engineering teams and mentor verification engineers.

Experience Level

Senior-level. The role requires 10+ years of experience in digital and/or mixed-signal design verification.

Responsibilities

Primary responsibilities include planning, implementing, and closing verification activities for complex memory and SoC projects.

• Verify IP, subsystem, full-chip, and system-level HBM and DRAM designs for functionality, performance, power, and quality.
• Develop verification plans from architecture and functional specifications in collaboration with architecture and design teams.
• Create and maintain verification environments, UVM testbenches, test suites, and automated regression infrastructures.
• Define and execute coverage-driven verification strategies to meet functional, assertion, and code coverage goals.
• Lead debug and root-cause analysis of complex design issues and drive bug resolution toward verification closure.
• Apply advanced digital and mixed-signal verification methodologies using industry-standard simulation and verification tools.
• Drive improvements in verification methodology, automation, regression efficiency, and AI-assisted verification workflows.
• Collaborate with global design, architecture, product, and system engineering teams to ensure project execution.
• Lead verification efforts for major HBM programs and mentor engineers through technical leadership and knowledge sharing.

Requirements

Must-have technical skills and experience required to perform the role.

• 10+ years of experience in digital and/or mixed-signal design verification with delivery of silicon products.
• Strong expertise in SystemVerilog, UVM, assertion-based verification (SVA), and coverage-driven methodologies.
• Experience debugging complex design and verification issues in large-scale ASIC, SoC, or memory designs.
• Strong understanding of CMOS circuit design fundamentals.
• Proven analytical, problem-solving, communication, and cross-functional collaboration skills.
• Experience with AI-assisted verification flows and automation.

Nice-to-have / Preferred:

• Experience or strong understanding of DRAM and/or HBM architecture, protocols, memory subsystems, and HPC applications.
• Familiarity with analog and digital simulation tools (example: HSPICE, mixed-signal simulators) and Verilog-based flows.
• Proficiency in Python, Perl, or similar scripting languages for verification automation and data analysis.
• Experience developing scalable verification infrastructures and automation frameworks.
• Demonstrated technical leadership, mentoring, and ability to influence verification methodology and cross-functional execution.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.