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Principal Design Verification Engineer – CPU Coherent Interconnect

SiFive
August 16, 2026
Full-time
On-site
Santa Clara, California, United States
$231,444 - $282,876 USD yearly
Verification Jobs, Level - Senior

Job Title

Principal Design Verification Engineer – CPU Coherent Interconnect

Role Summary

Lead verification strategy and execution for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms. Act as a principal technical lead working across architecture, RTL, formal, performance, and verification teams to ensure protocol correctness, ordering, flow control, arbitration, QoS, and subsystem integration.

Experience Level

Senior level — Principal. Requires deep, hands-on verification experience; the posting specifies 12+ years of relevant experience.

Responsibilities

The role is responsible for planning, executing, and closing verification for coherent interconnects from block-level through subsystem signoff.

  • Lead verification planning and execution for cache-coherent interconnects through integration and signoff.
  • Define verification strategy, test plans, assertions, checkers, scoreboards, stimulus approaches, and coverage models for coherency, ordering, backpressure, flow control, buffering, arbitration, QoS, and error handling.
  • Develop directed and constrained-random scenarios to expose corner cases in coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic.
  • Drive verification across interfaces, bridges, protocol adaptation layers, and subsystem data paths.
  • Partner with architecture, RTL, and formal teams to resolve specification ambiguity and improve debugability and verification completeness early in the cycle.
  • Perform root-cause analysis across spec, RTL, assertions, test content, and infrastructure; push issues to durable closure.
  • Apply appropriate verification methods (simulation, formal, emulation, performance verification) as required for signoff.
  • Influence methodology and infrastructure across the broader interconnect verification effort and mentor other engineers.

Requirements

Must-have technical skills and experience for the role; preferred items listed separately.

  • 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification at a principal/technical-lead level.
  • Strong hands-on experience with SystemVerilog-based verification and reusable verification infrastructure for complex hardware subsystems.
  • Deep understanding of cache-coherent systems, on-chip interconnects, CPU memory-subsystem behavior, and verification of ordering, snooping, and flow-control semantics.
  • Experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows for subsystem-level designs.
  • Strong debug skills and ability to translate architectural intent into verification strategy and execution.
  • Proficiency in software, scripting, and automation (Python or similar) for scalable DV infrastructure and workflows.
  • Strong technical communication and experience working across architecture, RTL, formal, performance, and verification teams.

Preferred / nice-to-have:

  • Direct experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance CPU or SoC environments.
  • Experience with large subsystem integration challenges involving coherent traffic, ordering, arbitration, QoS, error handling, and bridge-heavy designs.
  • Experience with memory consistency, weak ordering, and multicore coherency verification.
  • Experience with formal verification, emulation, or performance-oriented verification for subsystem signoff.
  • Demonstrated technical leadership through mentoring and influencing methodology across teams.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.


About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.

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Date Posted: 2026-08-14