Principal Design Verification Engineer

Job Title

Principal Design Verification Engineer

Role Summary

Lead verification strategy and execution for complex HUB/Router front-end IP within AMD's IOHUB team. Provide technical leadership for a global verification organization, drive verification methodology, and introduce AI-enabled methods to improve verification quality, productivity, and debug efficiency.

This role partners with architecture, design, emulation, firmware, and AI/tooling teams to ensure scalable, coverage-driven verification across product generations.

Experience Level

Senior (Principal-level technical leader). Specific years of experience not specified.

Responsibilities

Accountable for verification strategy, team leadership, and practical adoption of AI/automation within production DV environments.

• Define and own DV test plans and methodologies for HUB/Router designs to ensure scalability across variants and future generations.
• Collaborate with architecture, design, emulation, firmware, and subsystem verification leads to build end-to-end verification strategies.
• Identify and lead AI/ML-assisted verification initiatives (regression triage, failure clustering, coverage gap analysis, stimulus optimization, debug summarization).
• Work with AI/tool developers to pilot, measure, and scale tools; define success metrics and guide responsible adoption.
• Use data, dashboards, regression trends, and failure signatures to inform verification planning, execution, and closure.
• Mentor DV leads and engineers across global sites and help teams adopt AI-enabled tools while maintaining engineering ownership and quality.
• Anticipate verification closure and architecture risks; drive systemic solutions to protect schedule, quality, and coverage.
• Influence cross-functional technical decisions through analysis and clear communication.

Requirements

Must-have technical skills and leadership capabilities; preferred items are noted as such.

• Must-have: Deep verification expertise in large-scale, coverage-driven DV and verification closure strategy.
• Must-have: Proven technical leadership and ability to collaborate across architecture, design, emulation, firmware, and verification teams.
• Must-have: Experience with debug infrastructure, emulation, and managing verification for complex IP or subsystem-level designs.
• Nice-to-have: Hands-on interest or experience applying AI/ML tools to verification tasks (regression triage, failure clustering, stimulus generation, debug assistance).
• Nice-to-have: Scripting, data analysis, automation frameworks, prompt engineering, or workflow orchestration experience.
• Nice-to-have: Familiarity with PCIe protocol-layer verification, HUB/Router fabrics, coherency, or virtualization.
• Strong communication, documentation, planning, and ability to influence technical direction across global teams.

Education Requirements

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related discipline.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.