Principal Design Verification Engineer
MicrosoftJob Title
Principal Design Verification Engineer
Role Summary
Lead pre-silicon verification for custom IP and SoC designs on the Artificial Intelligence System on Chip (AISoC) team within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE). Drive verification strategy, testbench and UVM component development, coverage closure, and cross-functional technical delivery for cloud hardware.
Experience Level
Senior. Experience guidance by education path: PhD +3 years technical engineering experience, Master's +6 years, Bachelor's +8 years, or equivalent experience. Preferred: 12+ years in design verification and 5+ years in lead roles.
Responsibilities
Technical and hands-on responsibilities for pre-silicon verification of IP and SoC components.
- Technically lead a pre-silicon verification team focused on architectural and micro-architectural features.
- Define verification strategy and write test plans covering requirements and test environments.
- Design, write, execute, and debug constrained-random stimulus, scoreboards, checkers, and assertions.
- Develop and maintain UVM components and interfaces between tests and simulation environments.
- Collaborate across teams to enable vertical and horizontal reuse of verification components.
- Define and implement functional coverage models and drive coverage closure.
- Diagnose and triage testbench, simulation, and emulation failures.
- Develop and maintain makefiles and scripts for verification infrastructure.
- Apply Agile practices including code reviews, sprint planning, and feature deployment.
- Provide mentorship and technical leadership to engineers on the team.
Requirements
Must-have technical skills and program constraints. Education and degree-based experience thresholds are summarized separately under Education Requirements.
- Proven experience in design verification across multiple product cycles: test-plan creation, test development, debugging, and coverage signoff.
- Strong experience with Universal Verification Methodology (UVM) and testbench development; proficiency in C++ for verification environments.
- Experience debugging RTL, simulation, and/or emulation environments.
- Proficiency with scripting languages such as Python or Perl and with writing build/infrastructure scripts.
- Hands-on experience with formal property verification.
- Technical leadership experience, including leading cross-functional or cross-time-zone engineering teams and mentoring engineers.
- Ability to work with Agile development processes (code review, sprints, feature rollout).
- Must be able to meet Microsoft security screening requirements and export-control eligibility (citizenship or permanent-resident verification as required for access to controlled information).
Nice-to-have:
- Verification lead experience for IP or subsystems related to CPUs, VPUs, GPUs, DMA engines, Tensor units, or similar.
- Experience on AI/ML SoCs.
- Experience across verification for multiple silicon product cycles and leadership in coverage closure.
Education Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years technical engineering experience; OR Master's in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years technical engineering experience; OR Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years technical engineering experience; OR equivalent experience.
About the Company
Company: Microsoft
Headquarters: Redmond, Washington, United States
Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.
