Principal Design Engineer - Layout Design

Job Title

Principal Design Engineer - Layout Design

Role Summary

Lead and execute custom layout for high-speed and analog IPs, including SerDes, DDR/GDDR/LPDDR, PCIe, HBM, chiplets and other next-generation blocks. Work with circuit, digital, packaging and foundry teams to deliver production-ready analog macros and IPs.

The role includes individual contributor work on complex layouts and, depending on experience, leading a team of layout engineers to ensure timely IP delivery and verification compliance.

Experience Level

Senior — typically 8–11 years of relevant experience (or equivalent relevant experience).

Responsibilities

Primary responsibilities include design, verification and cross-team integration for analog/high-speed IP.

• Perform custom layout for high-speed and analog IPs (SerDes, DDR/GDDR/LPDDR, PCIe, HBM, chiplets, etc.).
• Interpret requirements from circuit design, digital, packaging and foundry teams; implement layouts to meet functional and integration constraints.
• Perform full-spectrum physical verification as per foundry requirements: DRC, LVS, electrical checks, ageing and reliability compliance.
• Define floorplan constraints and integrate analog IP at chip level.
• Analyze layout effects on circuit performance (speed, capacitance, power, area) and apply matching/shielding techniques.
• Lead and mentor layout engineers and coordinate cross-functional delivery when required.
• Adapt designs to new process nodes and changing foundry/market requirements.

Requirements

Core skills and experience required; items labeled as Nice-to-have follow.

• Must-have: Hands-on layout experience on high-speed analog IP and classical analog blocks (data converters, power management, PLLs, op-amps, bandgaps, LDOs).
• Must-have: Strong knowledge of analog layout techniques (matching, shielding), floorplanning and chip-level IP integration.
• Must-have: Experience with physical verification flows (DRC/LVS/electrical checks) and foundry compliance.
• Must-have: Strong communication, documentation and presentation skills; ability to work across teams and geographies.
• Nice-to-have: Experience on advanced process nodes (7nm, 5nm, 3nm, 2nm, 18a) and scripting/automation for layout flows.
• Nice-to-have: Leadership or mentoring experience leading a small team of layout engineers.
• Strong analytical and problem-solving skills; attention to detail in verification and integration tasks.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronic engineering (BE/BTech/ME/MS/MTech) or equivalent practical experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.