Principal Design Engineer — Design Verification

Job Title

Principal Design Engineer — Design Verification

Role Summary

Lead verification engineer responsible for subsystem and SoC-level functional verification, testbench architecture, and delivering silicon-ready designs. Works across architecture, design, and validation teams to define verification strategy, achieve coverage goals, and resolve complex hardware/verification issues.

Provides technical leadership and mentorship to less-experienced engineers and drives metric-driven verification practices to meet project timelines.

Experience Level

Senior (Principal level). Years-of-experience guidance not specified.

Responsibilities

The role owns verification architecture, implementation, execution, and debug for complex modules or significant subsystem/SoC blocks.

• Define verification architecture and strategy for subsystem/SoC projects.
• Design and develop scalable SystemVerilog/UVM testbenches from scratch.
• Develop verification test plans and implement testcases to meet functional and code coverage goals.
• Write C-based testcases and debug test failures at subsystem/SoC level.
• Apply metric-driven verification and maintain high-quality verification artifacts.
• Collaborate with architects, designers, and internal/external stakeholders to meet delivery timelines.
• Mentor and coach junior engineers to become independent verification contributors.

Requirements

Must-have technical skills and experience required to perform the role.

• Must-have: Subsystem/SoC verification experience with strong debug skills.
• Expertise in SystemVerilog and UVM-based verification methodologies.
• Experience architecting and implementing scalable verification environments and defining verification strategy.
• Proven experience developing verification test plans, coding testcases, executing and debugging to reach coverage targets.
• Experience with ARM-based designs and C-based testcase development.
• Strong knowledge of AMBA protocols (AXI, ACE, APB, AHB) and at least one of USB/PCIe/Ethernet/DDR/LPDDR or similar protocols.
• Demonstrated ability to work across cross-functional teams and mentor junior engineers.
• Nice-to-have: Prior experience with Cadence tools and flows, assembly programming, UART/I2C/SPI/JTAG familiarity, embedded C development, and formal verification experience.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.