Principal Design Engineer
Responsible for IR/EM signoff and power‑delivery network (PDN) optimization for advanced process nodes. Works with place-and-route, verification, and cross‑functional teams to ensure chip- and block-level power‑grid integrity during signoff.
Senior — 7 to 15 years of relevant experience in IR/EM/PDN signoff.
Primary responsibilities include power-integrity analysis, driving fixes during signoff, and automation to improve efficiency.
Must-have skills and experience.
BE / BTech / ME / MTech or equivalent engineering degree.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
