Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Lead architecture and implementation of the internal NAND datapath between the page buffer and IO, including wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair and clocking. Work within Micron's Non-Volatile Engineering Group (NVEG) to accelerate design and verification workflows using AI and drive technical direction across teams.

Experience Level

Senior - typically requires 8+ years of relevant experience in memory datapath, SRAM or high-speed custom design.

Responsibilities

Design, verify and lead improvements to internal datapath and timing methodologies; champion AI-driven workflows and semi-custom STA-based flows.

• Define, design and verify internal datapath blocks (page buffer-to-IO buses, wave pipelines, FIFOs, SER/DES front ends, datapath clocking) to meet bandwidth, timing and power targets.
• Architect and close wave-pipelined and flop-to-flop timing paths, managing setup/hold, skew/jitter, PVT margins and delay trims across PVT and aging.
• Design and verify dataline sensing (sense amps, precharge/latch sensing) with Monte Carlo/high-sigma margin analysis, coupling and IR drop considerations.
• Design column repair, fuse/repair storage and redundancy muxing; verify repair configurations with test, PE and firmware impacts in mind.
• Use AI for RTL generation, scripting, timing and waveform analysis; develop AI-processable specs, checklists and automation agents for timing and coverage checks.
• Lead transition from SPICE-only closure to semi-custom flows (characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, synthesis/APR/ECO).
• Drive physical co-design: floorplanning, bus routing, RC-aware delay matching and post-layout timing correlation with layout teams.
• Provide technical leadership: define interfaces with cross-functional teams, support silicon debug and mentor engineers.

Requirements

Must-have technical skills and proven experiences.

• 8+ years of experience in memory datapath, SRAM or high-speed custom design.
• Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin).
• Experience in dataline sense amp or SRAM read/write design, including Monte Carlo/high-sigma verification and margin analysis.
• Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation.
• Daily hands-on use of AI tools with concrete examples (prompts, scripts or agents) that improved productivity or design outcomes.

Nice-to-have:

• NAND/DRAM/SRAM periphery experience (page buffer, column decoder, global data bus, array-to-IO pipeline).
• Memory repair and redundancy design with yield/area/timing/test-time considerations.
• Timing-adjustment techniques (delay trims, DLL/DCC, training) and understanding of aging effects (NBTI/HCI).
• Experience building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug.
• Advanced CMOS device physics, mismatch modeling (BSIM) and low-power techniques (clock/power gating, leakage).
• Familiarity with STA and semi-custom flows mixing custom and standard-cell logic.

Education Requirements

Posting specifies a BS or MS in Electrical Engineering or a related field. The role pairs this academic expectation with a requirement for 8+ years of relevant industry experience. No certifications or explicit "equivalent experience" phrasing was provided.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.