Principal Design Engineer
Implement and verify high-capacity hardware-assisted verification SoCs (Palladium and Protium), focusing on physical implementation, timing closure, and tape-out for complex SOCs. Work across RTL synthesis, floorplanning, clock-tree design, timing/IR closure, and physical verification while coordinating with front-end and back-end teams.
Senior β Principal-level role. Candidates typically have 7+ years of relevant SoC physical design and implementation experience.
Primary responsibilities include:
Must-have technical skills and experience:
BS in Electrical Engineering with a minimum of 7 years' experience, OR MS with a minimum of 5 years' experience, OR PhD with a minimum of 1 year of experience (as specified in the posting).
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
