Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Lead verification strategy and execution for customer ASIC/SoC projects. Work on verification architecture, testbench development, and sign-off across RTL, gate-level, and low-power flows.

This role sits on the design verification team and requires technical leadership, customer interaction, and cross-functional coordination with design, architecture, and emulation groups.

Experience Level

Senior - typically requires 8–10 years of hands-on design verification (DV) experience in semiconductor, ASIC, or SoC companies.

Responsibilities

Accountable for verification strategy, execution, and delivery for small to mid-sized ASIC engagements.

• Define verification strategy and methodology (UVM/SystemVerilog) and select tools and infrastructure.
• Design scalable, reusable testbench architectures (BFMs, monitors, scoreboards, checkers).
• Translate architecture/specifications into verification plans and extract critical features and corners.
• Lead DV execution and customer-facing technical interactions; convert high-level requirements to an execution plan.
• Develop complex test cases and constrained-random sequences to achieve functional coverage goals.
• Perform root-cause analysis and debug complex design issues; collaborate with design engineers on fixes.
• Apply formal verification to prove properties and find deep bugs; oversee gate-level (GLS) simulation and power-aware checks.
• Monitor coverage metrics, define sign-off criteria, and provide final verification approval.
• Mentor junior engineers and coordinate across teams to manage schedules, risks, and priorities.

Requirements

Key technical and practical requirements for immediate productivity in this role.

• 8–10 years of hands-on design verification experience in semiconductor/ASIC/SoC companies.
• Deep expertise in SystemVerilog and UVM.
• Strong understanding of digital design fundamentals: RTL, timing, clocking, resets.
• Experience with industry simulators such as Xcelium, VCS, or Questa.
• Proficiency in coverage-driven verification: functional, code, and toggle coverage.
• Hands-on experience with formal verification tools and flows.
• Familiarity with common bus protocols (AXI, AHB, APB, PCIe, DDR, or similar).
• Strong debug skills including waveform analysis (Verisium, SimVision).
• Familiarity with low-power verification (UPF/CPF) and power-aware gate-level simulation.
• Ability to lead customer technical engagements and mentor junior engineers.

Education Requirements

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or a related field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.