Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

The Principal Design Engineer in NVEG leads datapath circuit design for NAND flash memory products, focusing on architecture, layout, timing, and signal/power integrity for high-speed, 3D-stacked memory interfaces. The role drives cross-functional technical decisions, leads design projects, and supports post-silicon validation and yield improvement.

Experience Level

Senior — typically requires 8+ years of relevant experience.

Responsibilities

Accountable for architecture, design, verification, and validation of internal datapath and TSV interfaces:

• Design and optimize TSV interface circuits (Rx/Tx), impedance matching, and timing margin analysis.
• Develop TSV electrical models and define circuit constraints for datapath interfaces.
• Specify signal integrity and power integrity requirements for wide parallel buses and TSV channels.
• Design TSV-specific DFT features: loopback tests, continuity checks, redundancy/remapping.
• Architect internal datapath from page buffer through sense amp, redundancy logic, bus driver to TSV output.
• Develop clocking and synchronization strategies including wave-pipeline design and skew management.
• Define timing budgets and perform timing analysis across datapath under PVT variations.
• Collaborate with process, DTCO, packaging, PE, apps, and integration teams; support post-silicon debug and tape-out revisions.

Requirements

Key technical and leadership requirements.

Must-have:

• 8+ years of experience in memory circuit design (DRAM, NAND, or other high-density memory technologies).
• Experience designing TSV or high-speed memory interfaces (e.g., NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4) including timing analysis, parasitic modeling, and signal integrity.
• Deep understanding of wide parallel bus performance, power and area optimization, clock distribution, skew management, and energy-per-bit tradeoffs in 3D-stacked memory.
• Proven ability to manage multi-block circuit design projects and communicate design trade-offs and schedules to technical and non-technical stakeholders.

Nice-to-have:

• Hands-on experience applying AI to design automation or quality improvement.
• Chip-level PDN optimization, CMOS device and reliability understanding, BSIM modeling for high-speed IO.
• Experience with signal/power integrity, power delivery network design, and physical design collaboration.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering is specified; the posting indicates candidates typically hold a BS/MS in Electrical Engineering and have 8+ years of experience in memory circuit design. No equivalent-experience alternative was provided.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.