Principal Collateral Device Engineer

Job Title

Principal Collateral Device Engineer

Role Summary

Lead development of device and interconnect collateral for advanced CMOS process nodes within Manufacturing Development and Customer Engineering (MDCE). The role coordinates across Process Integration, Yield, Device, and Design teams to define design rules, test structures, and process-monitoring layouts that ensure device performance and manufacturability.

Experience Level

Senior-level — requires extensive experience. The posting specifies 15+ years in CMOS device engineering focused on test chip design and device collateral development.

Responsibilities

Key responsibilities include designing and validating device collateral and enabling design rules for advanced process technologies.

• Define and validate derivative architectures, design rules, transistors, and interconnect requirements.
• Design test chips, scribe-line layouts, and process-monitoring structures for advanced nodes.
• Develop and manage design rule validation and waiver processes.
• Serve as the technical interface between Process Integration, Yield, Device, and Design teams (DTCO), including SRAM and standard-cell considerations.
• Apply design of experiments (DOE) and statistical methods to optimize device collateral.
• Analyze test-chip data using scripting, data analysis, and statistical techniques; drive data-informed decisions.
• Contribute to DRC/physical verification and mask-generation knowledge transfer to manufacturing and design teams.
• Work collaboratively in global, cross-disciplinary teams to deliver collateral solutions in a high-volume manufacturing environment.

Requirements

Minimum and preferred technical experience and skills. Education details appear under Education Requirements below.

• 15+ years experience in CMOS device engineering with emphasis on test chip design and device collateral development.
• Deep understanding of CMOS device physics, advanced transistor architectures (FinFET, GAA), and DTCO considerations.
• Experience with scribe-line layout design and process-monitoring structure development for advanced nodes.
• Proven skills in design rule development, validation, waiver management, and physical verification/DRC flows.
• Strong data analysis, scripting, and statistical process control (SPC) skills; experience applying DOE principles.
• Experience in high-volume manufacturing, yield monitoring, and process control structures.
• Ability to lead cross-functional teams and balance design-rule compliance with customer needs.
• Nice-to-have: hands-on experience with 3nm–16nm FinFET and sub-3nm GAA test-chip optimization and mask generation (Boolean/OPC).

Education Requirements

Minimum: Master’s degree in Electrical Engineering, Physics, or a related field. Preferred: Ph.D. in Electrical Engineering, Physics, or a related field. (The posting specifies these degrees explicitly.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.