Principal ATE Test Development Engineer

Job Title

Principal ATE Test Development Engineer

Role Summary

Lead test development engineer in the Operations group responsible for developing and validating test programs and methodologies for Marvell silicon. Collaborate with design, product, and DFT/DFM teams to ensure testability, yield, and that products meet customer specifications.

Experience Level

Senior - expects significant hands-on ATE test development experience, specifically with Advantest 93K test program development (see Requirements for details).

Responsibilities

Primary responsibilities include developing, validating, and releasing production test programs and improving test flows.

• Develop characterization, production, and wafer-sort test programs on the Advantest 93K platform.
• Design and validate tester hardware for high-speed testing.
• Create detailed test plans, methodologies, and documentation to meet product specifications.
• Perform test pattern conversion from design simulation environments to ATE formats.
• Lead test flow optimization: reduce test time, manage insertion/removal of tests, and improve yield.
• Work with DFT/DFM and product engineers on testability reviews and yield improvement actions.
• Develop new testing strategies or code when existing equipment capabilities are exceeded.
• Operate effectively in a fast-paced environment and manage multiple concurrent tasks.

Requirements

Must-have technical skills and experience; concise list of critical qualifications.

• Minimum 6+ years of test program development experience on the Advantest 93K ATE platform.
• Demonstrable ATE testing experience, test methodology, and silicon process knowledge.
• Experience with DFT/DFM and high-speed digital testing (4+ years indicated for high-speed testing).
• Proficiency in C/C++, Perl, and Python and comfortable in a Linux environment.
• Strong problem-solving, communication, teamwork, and interpersonal skills.
• Proven ability to lead release of production test programs and execute test flow optimization.
• High sense of urgency, accountability, and ability to multi-task in a fast-paced setting.

Nice-to-have: tester hardware design experience, in-depth characterization and wafer-sort expertise.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of related professional experience; or a Master's degree in Computer Science, Electrical Engineering, or a related field with 3–5 years of experience. (Degrees and field-of-study explicitly listed in the source.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.