Principal ASIC Design Engineer

Job Title

Principal ASIC Design Engineer

Role Summary

Primary digital contributor on a small senior ASIC team developing high-speed interface PHY test chips. Own the RTL micro-architecture and front-end digital implementation, drive synthesis and timing closure, and act as the principal interface between digital logic and analog/layout teams through tape-out.

Experience Level

Senior level. The role requires approximately 7–12 years of ASIC design experience, including at least one complete front-to-back tape-out.

Responsibilities

Deliver digital design and handoff for PHY-focused ASICs; coordinate with analog, layout, verification, and lab teams.

• Define micro-architecture and implement synthesizable SystemVerilog RTL for control, CSR/register files, clocking, management interfaces, and state machines.
• Create block-level architecture specifications and interface control documents; own design intent and CDC strategy.
• Perform logic synthesis and optimization (Design Compiler or Genus) to meet PPA targets.
• Develop and maintain SDC constraints; run and close static timing analysis (PrimeTime or Tempus) across corners and modes.
• Provide synthesized netlists, constraints, floorplan guidance, and documentation to layout/physical implementation teams; review placement/timing results and resolve RTL-rooted issues.
• Self-verify RTL with block-level simulation and waveform debug; write SystemVerilog Assertions for critical control sequences.
• Support GLS/timing simulation and lab bring-up with released netlists, parasitics, and register-level debug.
• Maintain design documentation, SDC rationale, ECO history, and implementation guidance.

Requirements

Must-have technical skills and experience. Preferred items are listed separately.

• 7–12 years of ASIC design experience with at least one front-to-back tape-out.
• Proficiency in synthesizable SystemVerilog RTL design with clean, documented coding practices.
• Hands-on experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing tools (PrimeTime or Tempus).
• Experience with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level verification.
• Practical knowledge of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent).
• Ability to translate digital design intent into actionable guidance for analog and layout engineers; effective cross-discipline collaboration.
• Strong written communication skills for producing specifications and documentation.
• Proficiency leveraging AI tools to improve productivity in design, debug, and documentation workflows.

Preferred (nice-to-have)

• Experience with place-and-route (Cadence Innovus or equivalent) and physical verification sign-off (Mentor Calibre).
• Experience in mixed-signal/custom design teams and PHY-adjacent implementations (SerDes, DDR, or equivalent).
• Familiarity with DFT, scan insertion, ATPG planning, PRBS generators, error counters, and silicon characterization infrastructure.
• Experience with GLS flows using Liberty models and SPF parasitics; familiarity with formal verification tools (JasperGold or VC Formal).
• Prior experience in small or startup-like teams where individuals carry large scope.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related technical field (BS, MS, or PhD in EE/CE or related).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.