Principal ASIC Architect

Job Title

Principal ASIC Architect

Role Summary

Lead the architecture definition and design of Tensordyne's next-generation ASIC family for generative AI inference acceleration. The role combines high-level silicon architecture planning with hands-on design, prototyping, and technical leadership to deliver multi-chip, data-center class AI processors.

Experience Level

Senior — requires substantial senior-level experience (posting specifies 15+ years of relevant silicon and architecture experience).

Responsibilities

Accountable for architecture, specification, modeling, and cross-functional delivery of high-performance AI processors.

• Define processor architecture including AI compute cores, embedded memory, RISC-V CPU cores, SerDes, HBM and PCIe connectivity, and chip-to-chip networking.
• Analyze system requirements and produce detailed design specifications and architectural models.
• Establish ASIC development milestones and ensure functionality, performance, power efficiency, programmability, debuggability, and manufacturability targets are met.
• Prototype and validate ASIC concepts using architectural C-models, SystemC or TLM and performance modeling.
• Lead design reviews, provide technical guidance, and mentor ASIC design and verification teams.
• Coordinate with external engineering partners, physical design teams, software teams, product management, and executives.
• Evaluate new silicon IP, EDA tools, and methodologies to improve product and design efficiency.

Requirements

Must-have qualifications, skills, and experience.

• 15+ years of hands-on experience in silicon design engineering and architecture of high-performance compute processors (GPU/CPU/TPU-class).
• Deep expertise with HBM, high-speed SerDes, and high-speed chip-to-chip networking technologies.
• Strong understanding of generative AI models (transformers, attention mechanisms) and how to map them to hardware.
• Proficient in Verilog; experience with RTL verification, performance analysis, debugging, and optimization.
• Experience developing architectural C-models, SystemC, or TLM; expert-level C/C++ and scripting (Python or Perl) for automation and modeling.
• Proven track record leading architecture definition, cross-discipline collaboration, and mentoring engineering teams.
• Ability to work with external partners and vendors; occasional travel required.

Nice-to-have:

• Experience with RISC-V integration, PCIe, and multi-chip scaling for data-center deployments.
• Familiarity with EDA toolchains and advanced physical design flows.

Education Requirements

Master's (MS) or PhD in Electrical Engineering, Computer Engineering, or a related engineering discipline.

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.