Principal Applications Engineer, Serdes Design IP

Job Title

Principal Applications Engineer, Serdes Design IP

Role Summary

Customer-facing technical role in the Technical Field Organization focused on pre-sales, configuration, and demonstration of Cadence Serdes PHY and controller IP. The role architects interface solutions for customers using high-speed protocols (PCIe, CXL, Ethernet, USB, etc.) and drives internal initiatives to improve team productivity and grow the IP business.

Experience Level

Senior - requires extensive industry experience. Typical guidance: MS + ~10 years or BS + ~15 years of relevant experience (see Education Requirements for details).

Responsibilities

Principal responsibilities include technical pre-sales support, customer enablement, and cross-functional collaboration to win IP opportunities.

• Own technical pre-sales and configuration for high-speed interface IP (PCIe, CXL, Ethernet PHY and Controllers).
• Present Cadence IP portfolio and demonstrate IP performance to prospective customers and at industry events.
• Act as product expert for digital controllers and PHY IPs and relevant protocols.
• Provide fast-turn, product-specific technical support to customers, field teams, architects, and designers.
• Collaborate with IP sales, marketing, and R&D to capture and win opportunities.
• Author application notes and technical articles for internal and external audiences.
• Define and lead initiatives to improve team processes and productivity; occasionally travel to customer sites.

Requirements

Must-have technical skills, experience, and abilities.

• Extensive hands-on experience with one or more high-speed interface protocols: PCIe, CXL, UCIe, Ethernet, USB, MIPI, 224G, 112G.
• Strong knowledge of PHY and/or controller design, integration, or application for high-speed interfaces.
• Experience in technical pre-sales, customer engagement, or solutions architecture for IP products.
• Demonstrated individual leadership, initiative, and ability to manage pre-sales accounts.
• Excellent verbal and written presentation and communication skills.

Nice-to-have:

• Lab validation and demo setup skills.
• Experience with controller and/or PHY verification.
• Knowledge of AXI and PIPE interface protocols.
• Practical working knowledge of high-speed PHY lab/debug techniques.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with ~15+ years of relevant experience, or Master's degree in EE/CE (or equivalent) with ~10+ years of relevant experience. The posting also allows equivalent practical experience in lieu of the degree-specific combinations.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.