Principal Applications Engineer

Job Title

Principal Applications Engineer

Role Summary

Serve as the primary technical interface between Marvell Central Engineering IP teams and customers to lead SerDes IP integration, silicon bring-up, and production support across ASIC and switch programs. The role coordinates cross-functional engineering resources and provides on-site customer support as needed. This is a hybrid position based in the Santa Clara office with occasional travel to customer sites.

Experience Level

Senior. See Education Requirements for degree and years-of-experience guidance.

Responsibilities

Core responsibilities include:

• Lead SerDes IP integration and customer bring-up from design review through silicon validation and production release, including kick-offs, risk assessments, and test plan alignment.
• Coordinate engineering resources across IP design, firmware, and validation teams to support SoC bring-up and production stability.
• Diagnose and resolve signal integrity issues, including equalization, link training, and FEC performance across multi-rate SerDes and supporting analog IPs.
• Analyze PCB layouts, perform channel simulations and S-parameter analysis to identify integration risks early.
• Use industry-standard high-speed test and compliance equipment to isolate and debug lab issues.
• Own customer technical escalations end-to-end, conduct root-cause analysis, and document resolutions.
• Prepare and deliver customer-facing technical collateral such as integration guides, application notes, and API documentation.
• Present program status and technical findings to customer engineering teams and internal leadership.
• Collaborate closely with IP design, DSP, firmware teams, SoC architects, and customer engineers to keep programs on schedule.

Requirements

Must-have technical skills and attributes:

• Proven hands-on experience with high-speed SerDes IP integration and silicon bring-up, including signal integrity analysis and end-to-end debug across complex SoC programs.
• Practical knowledge of SerDes equalization, link training, and FEC behavior.
• Experience with high-speed interfaces and standards such as Ethernet (10G–200G KR/CR/C2M/C2C), PCIe Gen1–Gen6, CPRI, JESD, and CEI.
• Skilled in PCB layout review, channel simulation, and S-parameter-based analysis.
• Proficiency with electrical characterization and compliance test equipment used for high-speed interfaces.
• Ability to manage multiple customer engagements independently and own the full technical lifecycle from integration kickoff through production.
• Strong written and verbal communication skills and experience presenting technical findings to customers and leadership.
• Willingness to travel occasionally to customer sites for bring-up and support.
• Must be eligible to access export-controlled technology; employment may be subject to export license review.

Nice-to-have:

• Prior work on switch, custom ASIC, or connectivity programs (PCIe, Ethernet, device-to-device).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 10–15 years of relevant experience; OR a Master's degree or PhD in Computer Science, Electrical Engineering, or related fields with 5–10 years of relevant experience. (No explicit equivalent-experience language provided.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.