Principal Application Engineer - Verification

Job Title

Principal Application Engineer - Verification

Role Summary

Senior technical role focused on SoC verification for complex subsystems and full‑chip environments. The engineer will own verification plans, build and maintain UVM‑based testbenches, debug integration issues, and work closely with design, architecture, and validation teams.

Experience Level

Senior — 6+ years of hands‑on digital SoC verification experience.

Responsibilities

Primary responsibilities include design and execution of verification activities across block, subsystem, and SoC levels:

• Develop and execute verification plans for complex SoC subsystems and full‑chip environments.
• Build, enhance, and maintain UVM‑based verification environments (agents, sequences, scoreboards, coverage models).
• Perform block‑, subsystem‑, and SoC‑level verification including integration, unit, and system tests.
• Verify integration of third‑party IP, custom logic, and system‑level features.
• Debug functional issues across RTL, testbench, and integration layers using waveform tools, assertions, and logs.
• Analyze coverage metrics, identify gaps, and drive closure for functional, code, and assertion coverage.
• Support bring‑up and validation on emulation/FPGA platforms when required.
• Contribute to improving verification methodologies, automation, and infrastructure; document test plans and reports.

Requirements

Core technical must‑have skills and selected nice‑to‑have items.

Must‑have:

• 6+ years of hands‑on digital SoC verification experience.
• Proficiency in SystemVerilog and UVM; constrained‑random and coverage‑driven methodology.
• Solid understanding of SoC architecture, memory hierarchy, cache systems, interconnects, and coherency concepts.
• Experience verifying application processors, AI accelerators, DSP, multimedia, or other high‑performance compute SoCs.
• Familiarity with industry protocols such as AXI, AHB, APB, PCIe, USB, DDR/LPDDR, MIPI, Ethernet, or similar.
• Hands‑on experience with simulation, emulation, or acceleration platforms and strong debugging skills.
• Ability to work effectively in cross‑functional, multi‑site teams and to communicate technical issues clearly.
• Self‑driven and detail‑oriented, able to work in a fast‑paced environment.

Nice‑to‑have:

• Knowledge of low‑power verification (UPF), formal verification, or performance validation.
• Familiarity with Python, Perl, or shell scripting for automation.
• Exposure to post‑silicon validation flows and DFT concepts (scan/MBIST).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.