Principal Application Engineer, Digital Implementation and Signoff

Job Title

Principal Application Engineer, Digital Implementation and Signoff

Role Summary

Principal Application Engineer on the Digital Implementation and Signoff team working with customers to deploy and optimize Cadence synthesis, place-and-route, and signoff flows. The role focuses on achieving PPA targets, improving design closure, driving tool adoption, and feeding customer requirements back to R&D.

Experience Level

Senior level — requires 10+ years of industry physical design experience.

Responsibilities

Primary responsibilities include:

• Provide technical support for backend digital design implementation and signoff, including place-and-route, timing and power closure, and IR drop.
• Advise customers on best use of tools and methodologies to meet project schedules and design goals.
• Conduct technical presentations, demonstrations, and drive evaluations/benchmarks to success.
• Collaborate closely with R&D to relay customer requirements and improve tools and flows.
• Develop and augment flows and automation using Tcl, Python, or other scripting languages.
• Capture and promulgate best practices and lessons learned from engagements.
• Drive adoption of Cadence tools and provide mentorship/guidance to customer teams and internal staff.

Requirements

Must-have:

• 10+ years of industry physical design experience.
• Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis.
• Experience with IC digital implementation flows and backend EDA tools (place-and-route, IR drop, timing and power closure).
• Experience with advanced nodes (10nm and below).
• Proficient in scripting languages such as Tcl, Perl, or Python.
• Strong customer-facing communication, problem-solving, and written skills.
• Self-motivated with a drive for continuous learning.

Nice-to-have:

• Experience with front-end EDA flows: synthesis, DFT, and logical equivalence checking.
• Familiarity with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC/ICC2, DC, or PrimeTime.
• Experience with advanced nodes (5nm and below).

Education Requirements

BS in Computer Science, Computer Engineering, Electrical Engineering, or a related field is required; MS in a related field is preferred.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.