Principal Analog/Mixed-Signal CAD Engineer - EMIR

Job Title

Principal Analog/Mixed-Signal CAD Engineer - EMIR

Role Summary

Lead technical role on Marvell's Central Engineering CAD team responsible for developing and maintaining electromigration and IR-drop (EMIR) analysis and analog/mixed-signal (AMS) CAD infrastructure. The position supports advanced FinFET, BiCMOS, SiGe, and silicon photonics IC development and interfaces with design teams, foundries, and EDA vendors.

This role is based in Marvell's Santa Clara or Irvine office and requires onsite presence five days per week.

Experience Level

Senior-level. Relevant industry experience is expected; the posting specifies experience ranges tied to degree level (see Education Requirements).

Responsibilities

Primary responsibilities include building, validating, and supporting EMIR and AMS design flows and related automation.

• Develop and support EMIR analysis flows: DSPF validation, current-density and voltage-drop analysis, debugging, and post-layout verification.
• Architect and maintain next-generation automated AMS design flows used across Marvell design teams.
• Create and maintain custom tools, PCells/Pycells, GUI utilities, and automation using scripting languages within Cadence Virtuoso, Synopsys OptoCompiler, and Siemens Calibre environments.
• Install, validate, and support foundry PDKs and associated verification flows.
• Set up and maintain physical verification, parasitic extraction, and EMIR flows.
• Collaborate with analog designers, silicon photonics engineers, foundry partners, and EDA vendors to troubleshoot and resolve design-flow issues.
• Contribute to company-wide CAD infrastructure, best practices, and technical leadership for AMS and silicon photonics development.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• Hands-on experience with Cadence Voltus-XFi for EMIR analysis.
• Proven track record building and maintaining AMS design flows for advanced nodes (FinFET, BiCMOS, SiGe, SiPho).
• Strong hands-on experience with Cadence Virtuoso Studio, Synopsys OptoCompiler, and Siemens Calibre.
• Solid understanding of AMS flows: schematic capture, simulation, parasitic extraction, post-layout verification, and EMIR debugging.
• Programming/scripting proficiency: Python, TCL, Shell, and SKILL.
• Experience developing CAD automation or verification frameworks and custom tooling.
• Experience installing/validating foundry PDKs and maintaining physical verification and extraction flows.
• Excellent communication and cross-functional collaboration skills.

Nice-to-have:

• Experience with electromagnetic (EM) simulation and extraction.
• Familiarity with silicon photonics design flows.

Education Requirements

Degree guidance provided in the posting: Bachelor of Science in Electrical Engineering (BSEE) with approximately 10–15 years of professional experience, or Master’s/PhD in Electrical Engineering with approximately 5–10 years of industry experience. No specific certifications were required in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.