Principal Analog Mixed Signal ASIC Layout Engineer

Job Title

Principal Analog Mixed Signal ASIC Layout Engineer

Role Summary

The analog mixed-signal (AMS) ASIC layout engineer will produce full-custom analog layouts, perform chip floor-planning, and support tape-outs for ASICs used in national security, biomedical, and space applications. The role works within the physical silicon design group and requires cross-disciplinary collaboration to meet performance, power, and reliability targets.

Experience Level

Senior-level. Posting specifies 5–7 years with a bachelor's degree, 3–5 years with a master’s degree, or 0–2 years with a PhD in ASIC hardware engineering or a related field.

Responsibilities

Primary responsibilities include design, verification, and physical implementation of analog/mixed-signal ASICs.

• Design and simulate transistor-level analog circuits to meet architecture and requirements.
• Perform chip-level floor-planning and full-custom physical layout for analog blocks and complete chips.
• Extract parasitics and simulate layouts to verify circuit performance.
• Optimize designs for performance, power, cost, and manufacturability (DFM/DFY considerations).
• Analyze and resolve complex layout and integration issues; drive solutions when requirements are unclear or change.
• Contribute to system-level design, architecture, and proposal activities as needed.
• Document and teach best practices; mentor less-experienced engineers.
• Support physical verification (DRC/LVS/PM) and participate in tape-out activities.

Requirements

Must-have technical skills and capabilities are listed first; preferred skills follow.

• Proven experience implementing analog designs in full-custom layout and performing chip-level floor planning.
• Proficiency with Cadence Virtuoso-based layout flows and physical verification tools (e.g., Pegasus, Calibre) and familiarity with extracted-parasitic simulation.
• Strong understanding of silicon processing and how layout affects circuit performance (matching, proximity effects, implant/shadowing, coupling, self-heating, EM/IR).
• Experience debugging DRC/LVS/PM results and applying fixes for manufacturability and reliability (ESD/LU, DFM).
• Ability to work independently, prioritize tasks, meet deadlines, and communicate technical issues across disciplines.
• Ability to obtain and maintain a U.S. government security clearance (required for selected applicants).

Nice-to-have:

• Low-power analog design experience, PLLs, ADCs/DACs, high-speed SerDes, bandgaps, ESD/IO blocks.
• Experience with advanced CMOS nodes (<32nm), FinFET (22–7nm), GAAFET, photonics, and radiation-hardened design.
• Experience with automation and data-transfer tools (Cadence ModGen/autorouter/EAD, Innovus) and scripting (SKILL, SVRF, Tcl).
• Familiarity with source-control systems (SOS, git, SVN) and Linux-based tool environments.
• Experience with reticle design and/or MPW aggregation.

Education Requirements

Required: Bachelor's degree in Engineering or a related technical field. Preferred: Master’s degree. PhD is acceptable. The posting provides equivalent-experience guidance: 5–7 years experience with a BS, 3–5 years with an MS, or 0–2 years with a PhD.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.