Principal Analog IC Design Engineer

Job Title

Principal Analog IC Design Engineer

Role Summary

Join Marvell's Central Engineering AMS IP team to design advanced CMOS transceivers, SerDes, PLLs, ADCs, regulators, amplifiers, TX/RX and CDR circuits. The role focuses on architectural investigations, circuit implementation, and verification to meet performance targets.

This position leads a team of analog design engineers, coordinates with layout, verification and application teams, and manages delivery of analog IP from concept through production, including pre-tapeout validation and lab silicon bring-up.

Experience Level

Senior; typically requires 6+ years of relevant analog IC design experience.

Responsibilities

Primary responsibilities include hands-on analog design, verification, team leadership, and delivery of high-speed analog IP.

• Perform architectural studies and implement analog circuits (PLL, DLL, ADC, regulators, amplifiers, TX/RX, CDR) to meet performance targets.
• Conduct design verification and simulations using tools such as SPICE, Spectre, and MATLAB.
• Lead and mentor a team of analog design engineers.
• Coordinate with layout, verification, and application teams to ensure manufacturability and system integration.
• Manage delivery of analog IP from concept to production, including pre-tapeout validation.
• Oversee lab chip bring-up, debugging, and silicon validation activities.
• Document designs and communicate technical trade-offs to stakeholders.

Requirements

Core technical skills and experience required; grouped as must-have and nice-to-have.

• Must-have: Proven analog IC design experience with PLLs, data converters, oscillators, and high-speed SerDes (receiver and transmitter designs).
• Must-have: Proficiency with analog design and verification tools (Virtuoso, Spectre, ADE, post-layout extraction).
• Must-have: Knowledge of signal integrity, noise reduction, and multi-GHz low-jitter clock generation and distribution.
• Must-have: Understanding of analog layout effects in FinFET processes and experience with system-level pre-tapeout validation and lab chip bring-up.
• Nice-to-have: Experience with 112G+ SerDes, especially short-reach and low-power designs.
• Nice-to-have: Experience with single-ended high-density parallel interfaces (UCIe, DDR5/LPDDR5); GDDR6/LPDDR6 is a plus.
• Nice-to-have: Strong communication and cross-functional collaboration skills.

Education Requirements

Master's or PhD in Electrical Engineering or a related field. The posting specifies 6+ years of relevant analog IC design experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.