Principal Analog Design Engineer (SERDES)
Cadence Design SystemsJob Title
Principal Analog Design Engineer (SERDES)
Role Summary
The Principal Analog Design Engineer will provide technical leadership for the PMA design team within a SERDES product team based in Cork, Ireland. The role covers full-cycle analog/mixed-signal IC design for high-speed SERDES products, from specification through verification and delivery.
Primary interactions include collaboration with physical-design engineers, cross-site engineering teams, and product leadership to meet customer electrical specifications.
Experience Level
Senior — minimum 7 years of experience in CMOS SERDES or high-speed I/O IC design and development.
Responsibilities
Key responsibilities focus on design, verification, and technical leadership for high-speed SERDES PMA sections.
- Design high-speed SERDES products at data rates up to and exceeding 112 Gbps on advanced technology nodes (e.g. 5nm FinFET CMOS).
- Develop analog/mixed-signal IC circuit blocks from concept and specification through final verification against customer requirements.
- Collaborate with Physical Design Engineers on IC circuit block and PMA section implementation.
- Provide technical leadership in circuit design and SERDES architecture decisions.
- Coordinate with global teams across multiple time zones (including US west and east coast).
Requirements
Must-have technical skills and experience required for successful performance in this role.
- Minimum 7 years experience in CMOS SERDES or high-speed I/O IC design and development.
- Working knowledge of common SERDES standards and their electrical requirements.
- Thorough understanding of jitter and signal equalization techniques.
- Proven design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low-jitter PLL, High-speed Clock Distribution, Bias and Bandgap, Voltage Regulators.
- Strong problem-solving skills, analog aptitude, and effective communication; ability to work cooperatively in a team environment.
Preferred:
- Experience with Cadence tools and design at >10 Gbps and in <40 nm technologies.
- Lab test and silicon-evaluation experience.
- Interest in publishing or presenting at technical conferences (e.g., ISSCC, JSSC).
Education Requirements
Candidates are expected to be BEng, MEng, or PhD qualified.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
