Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)

Job Title

Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)

Role Summary

Lead design and characterization of custom analog circuits for high-speed PHYs, with primary focus on clocking (PLL/DLL/CDR) and transmitter/receiver circuitry. Work within the Interface Pathfinding team to define analog architecture, own transistor-level implementation, and support post-silicon validation.

Experience Level

Senior level — typically requires 10+ years of analog/mixed-signal IC build experience and prior primary-ownership tape-out experience.

Responsibilities

Primary responsibilities include:

• Lead development of specialized analog blocks, focusing on clocking (PLL, DLL, CDR) and high-speed transmitter/receiver circuits.
• Define top-level PHY analog architecture, including clocking topology and signal-chain partitioning.
• Create and maintain transistor-level simulation testbenches; run process-corner, Monte Carlo, and mismatch analyses to assess margin and yield sensitivity.
• Specify clear interfaces between custom analog blocks and digital control wrappers.
• Collaborate with layout teams and lead post-silicon characterization activities in the lab.

Requirements

Must-have qualifications:

• 10+ years analog/mixed-signal IC build experience with at least one tape-out in a primary circuit ownership role.
• Deep expertise in clocking circuits (PLL, DLL, or CDR) and transistor-level implementation in advanced CMOS nodes.
• Strong transistor-level simulation skills (HSpice or equivalent); experience with corner, Monte Carlo, and mismatch analysis for yield-aware design.
• Proven understanding of jitter analysis and its impact on high-speed link timing margins.
• Ability to leverage AI/ML/LLMs to improve productivity and design efficiency.

Nice-to-have / preferred:

• Experience in high-speed transmitter design: output drivers, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or SerDes interfaces.
• Experience in receiver design: sense amplifiers, CTLE/DFE equalization, samplers, and threshold calibration.
• Familiarity with short-reach PHY architectures (UCIe, AIB, BoW) and die-to-die interfaces.
• Experience with OTP/fuse-based calibration architectures and analog trim loops.
• Post-silicon characterization experience correlating simulation to measured eye diagrams, BER curves, phase noise, and jitter histograms.

Education Requirements

BS, MS, or PhD in Electrical Engineering or a related technical field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.