Principal Analog Design Engineer, HBM

Job Title

Principal Analog Design Engineer, HBM

Role Summary

Lead design, integration, and delivery of advanced analog and mixed-signal IP for High Bandwidth Memory (HBM) logic dies. Provide technical leadership across analog design, IP integration, system alignment, and silicon execution to enable high performance, power efficiency, and reliability in HBM products.

Work cross-functionally with layout, digital, system, packaging, and test teams to drive analog subsystems from specification through silicon bring-up.

Experience Level

Senior — approximately 10–15+ years of analog/mixed-signal IC design experience.

Responsibilities

Key responsibilities include:

• Lead design and ownership of critical HBM analog circuits, including high-speed transmitters and receivers.
• Design and validate clock generation and distribution (PLLs, DLLs, CDRs) and SerDes-related analog blocks.
• Design biasing, reference, calibration, and power regulation circuits (LDOs, regulators).
• Define and manage IP interfaces, power domains, clocking schemes, and reset strategies across subsystems.
• Perform detailed pre-layout and post-layout simulations; run PVT, Monte Carlo, mismatch, and aging analyses.
• Collaborate with layout engineers on floorplanning, symmetry, matching, shielding, and EM/IR compliance; review and sign off analog layouts.
• Drive layout-aware design optimizations for advanced process nodes and define best practices for analog design, documentation, and reuse.
• Support silicon bring-up and lab validation; drive cross-team technical alignment through integration and testing phases.

Requirements

Must-have skills and experience:

• 10–15+ years experience in analog/mixed-signal IC design.
• Proven expertise in high-speed interface design, clocking circuits (PLL/DLL/CDR), and power management circuits.
• Experience with analog IP integration at subsystem or SoC level; strong SPICE simulation, extraction, and modeling skills.
• Hands-on experience with silicon bring-up and lab validation.
• Deep understanding of advanced CMOS processes and effects such as noise, jitter, SI/PI, and cross-domain coupling.
• Ability to perform pre-/post-layout analysis, PVT/Monte Carlo/mismatch/aging studies and implement layout-aware optimizations.
• Strong collaboration and communication skills to work across analog, digital, system, packaging, and test teams.

Nice-to-have:

• Knowledge of DRAM sub-system architecture, specification, and operation.
• Understanding of physical layout and circuit floor planning.
• Excellent problem-solving and analytical skills.

Education Requirements

MS or PhD in Electrical Engineering or a related field (specified in minimum qualifications).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.