Principal Analog Design Engineer

Job Title

Principal Analog Design Engineer

Role Summary

Senior analog/mixed-signal circuit designer on the Solution IP R&D team developing high-speed PHY IP for DDR/LPDDR, HBM, UCIe, and mobile storage. Responsible for transistor-level design, verification, layout interaction, and silicon bring-up to deliver reliable, power-efficient PHY sub-blocks in advanced FinFET nodes.

Experience Level

Senior-level (Principal).

Responsibilities

Primary responsibilities include:

• Define analog and mixed-signal sub-block specifications by interpreting JEDEC and relevant standards for memory and interconnect PHY IP.
• Design transistor‑level circuits such as equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgap references, ADCs, and DACs.
• Develop verification strategies using SPICE simulators and Verilog‑A models to ensure coverage across PVT corners and present simulation trade-offs.
• Collaborate with layout engineers to minimize parasitics, manage device stress, and implement ESD protection.
• Document circuit designs, test plans, and reliability considerations for tape‑out.
• Consult on electrical characterization and silicon bring‑up to validate circuits in silicon.
• Reduce tape‑out risk through early layout‑aware reviews and cross‑functional decision making.

Requirements

Must-have technical skills and experience:

• Deep expertise in transistor‑level CMOS design with strong fundamentals in device physics and matching.
• Proven experience designing in FinFET process technologies.
• Detailed experience with high‑speed sub‑circuits: equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgaps, ADCs, or DACs.
• Proficiency with schematic entry, SPICE simulation tools (e.g., Spectre, HSPICE), and Verilog‑A modeling.
• Working knowledge of ESD protection techniques and layout strategies; familiarity with layout‑dependent effects.
• Strong understanding of design‑for‑reliability including electromigration, IR drop, and aging.
• Ability to communicate design trade‑offs to internal teams and customers and to produce clear documentation for handoff.
• Scripting experience (Python, Perl, TCL, MATLAB, or C) to automate simulation flows and custom analyses.

Nice-to-have:

• Experience with silicon bring‑up and electrical characterization of PHY IP.
• Prior work on memory and interconnect standards (DDR/LPDDR, HBM, UCIe) or mobile storage PHYs.

Education Requirements

PhD with 6+ years or Master's with 8+ years of analog and mixed‑signal IC design experience. Emphasis on analog/mixed‑signal IC design and device physics in advanced FinFET technologies.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.