Principal Analog Design Engineer

Job Title

Principal Analog Design Engineer

Role Summary

Lead analog IP architecture and implementation for CMOS LR SerDes, device-to-device (D2D) and common analog IPs within Marvell's Central Engineering group in Bangalore. Manage a small analog team, coordinate with layout, verification and application teams, and drive designs from concept through tape-out to production.

Experience Level

Senior — 14+ years of experience.

Responsibilities

Typical duties include:

• Define architecture and implement circuits such as PLLs, DLLs, ADCs, regulators, amplifiers, TX/RX, CDRs and other analog building blocks to meet performance targets.
• Lead and mentor a team of analog design engineers and coordinate cross-functional interfaces (layout, verification, applications).
• Plan and manage delivery of analog IP from concept to production, including schedule and design reviews.
• Perform design verification and pre-tapeout system-level analog validation.
• Support lab chip bring-up and on-silicon debugging to resolve functional and performance issues.
• Drive signal integrity and noise-reduction techniques for multi-GHz low-jitter clock generation and distribution.

Requirements

Technical must-have and desired skills:

• Must-have: Extensive hands-on experience with D2D IP, PLLs, data converters, oscillators and high-speed SerDes (receiver and transmitter design).
• Must-have: Proficiency with analog design and verification tools such as Cadence Virtuoso, Spectre, ADE and post-layout extraction tools; familiarity with SPICE/Matlab workflows.
• Must-have: Strong understanding of signal integrity, noise reduction, and low-jitter clock generation/distribution at multi-GHz frequencies.
• Must-have: Practical experience with analog layout considerations in FinFET processes and their impact on high-speed designs.
• Must-have: Experience in system-level pre-tapeout validation, lab chip bring-up and debugging; strong communication skills.
• Nice-to-have: Experience with single-ended high-density parallel interfaces for chip-to-chip communication, UCIe, DDR5/LPDDR5, GDDR6/LPDDR6 or HBM.

Education Requirements

Preferred: Masters degree and/or PhD in Electrical Engineering or a related field. The posting specifies 14+ years of experience. No explicit equivalent-experience language or certifications were listed.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.