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Principal Analog Design Engineer

Qorvo
June 29, 2026
Full-time
Remote friendly (San Jose, California, United States)
Worldwide
$170,300 - $221,500 USD yearly
ASIC Design Jobs, Level - Senior

Job Title

Principal Analog Design Engineer

Role Summary

Lead architecture, design, and validation of high-performance analog power management integrated circuits (PMICs and DC-DC converters) within Qorvo's Power Management division. Deliver efficient, reliable, and manufacturable silicon by collaborating with system, layout, test, and global design teams.

Hybrid role with the expectation to be onsite multiple days per week at either the San Jose, CA or Richardson, TX office.

Experience Level

Senior-level. Requires approximately 12+ years of engineering experience, including at least 8 years in analog and mixed-signal IC design focused on power converters.

Responsibilities

Primary responsibilities include:

  • Lead design and development of high-performance analog power management ICs focused on efficiency, power density, and reliability.
  • Define product architecture and specifications with system engineers, balancing performance, power, and cost.
  • Select and implement circuit topologies and control methodologies; perform transistor-level design, simulation, and validation.
  • Collaborate with layout engineers to optimize floor planning, parasitics, and overall silicon performance.
  • Partner with test and characterization teams to define validation methodologies, troubleshoot issues, and optimize production test strategies.
  • Coordinate with global design teams and drive technical reviews and documentation for internal stakeholders.

Requirements

Must-have qualifications and skills:

  • Approximately 12+ years of engineering experience in the semiconductor industry, with at least 8 years in analog/mixed-signal IC design focused on DC-DC power converter architectures (voltage-mode and current-mode control).
  • Proven transistor-level design, simulation, and validation experience to meet functional and performance specifications.
  • Experience with EDA flows for parasitic extraction, EMIR/capacitive coupling analysis, and handling floating nodes.
  • Experience with production release of power management ICs and working with layout to address yield and manufacturability.
  • Ability to communicate technical concepts effectively to both technical and non-technical stakeholders.
  • Preferred tool experience: Cadence Virtuoso, Simplis, ADS; hands-on lab experience with switching power supplies is a plus.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering. Preferred: Master's or PhD in Electrical Engineering. The posting also allows equivalent combinations of education and relevant semiconductor industry experience.


About the Company

Company: Qorvo

Headquarters: Greensboro, NC, US

Qorvo supplies innovative semiconductor solutions that enhance connectivity and power for a variety of applications, including consumer electronics, automotive, and healthcare. With a focus on RF and power solutions, Qorvo combines technology leadership and global manufacturing to address complex challenges in fast-growing industries. Their commitment to excellence and innovation drives them to shape the future of wireless communications.

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Date Posted: 2026-06-28