Principal Analog Design Engineer

Job Title

Principal Analog Design Engineer

Role Summary

Lead full-custom analog design of electronic transceiver blocks that interface with custom silicon photonics for a production photonic AI platform. Work spans specification, transistor-level architecture, simulation, and tape-out-ready physical layout of GHz-speed analog circuits.

Collaborate closely with photonics and digital teams to optimize the electro-optic interface and support bench characterization and production testing.

Experience Level

Senior — typically 10+ years professional experience in full-custom analog integrated circuit design; 5+ years focused on GHz-speed RF or broadband analog design.

Responsibilities

Design and deliver high-speed analog blocks from specification through tape-out and characterization.

• Architect, simulate, and verify circuits such as high-swing drivers, transimpedance amplifiers, ADCs, DACs, and PLLs in deep-submicron CMOS.
• Perform full-custom schematic capture, advanced analog simulation, and physical layout using Cadence Virtuoso; execute DRC/LVS.
• Perform post-layout extraction and simulation to validate performance under parasitics.
• Ensure signal integrity and power integrity across high-speed interconnects and perform layout floor planning.
• Collaborate with Photonics and Digital teams to optimize electro-optic interface and system-level performance.
• Support bench characterization and production test development.

Requirements

Must-have technical skills and experience.

• 10+ years of professional experience in full-custom analog integrated circuit design; 5+ years in GHz-speed RF or broadband analog design.
• Expert proficiency with the Cadence tool suite (Virtuoso schematic, simulation, and custom layout).
• Deep understanding of semiconductor device physics, linearity, noise analysis, and high-frequency circuit theory.
• Proven track record of taking high-speed analog blocks from concept to successful tape-outs and production.
• Experience ensuring signal integrity and power integrity for high-speed designs.
• Practical experience with post-layout extraction and parasitic-aware verification.

Nice-to-have / preferred:

• Background in photonic transceivers or optical communication electronics.
• Experience in advanced TSMC nodes (N5P, N3P, N2P).
• Design experience with high-speed data converters and low-jitter clocking (PLLs).
• Familiarity with EM simulation tools (EMX, HFSS) and frequency-domain simulation (Spectre RF).

Education Requirements

MS or PhD in Electrical Engineering.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.