Principal Analog Circuit Design Engineer - SerDes

Job Title

Principal Analog Circuit Design Engineer - SerDes

Role Summary

Design and implement analog and mixed-signal SerDes circuits in advanced process nodes. Work within a cross-functional engineering team to deliver IP and integration-ready analog blocks, support silicon bring-up, and ensure designs meet power, performance, area, timing, and yield targets.

As a principal engineer, provide technical leadership, mentor engineers, influence technical direction, and drive execution to deliver products to market.

Experience Level

Senior level — Principal. Typical guidance: 8+ years of analog/mixed-signal SerDes design experience; deeper leadership roles often expect 10+ years.

Responsibilities

Primary responsibilities include:

• Architect, design, simulate, and optimize analog/mixed-signal SerDes circuits (PLL, CDR, CTLE, DFE, ADC, TX/RX).
• Define floorplans, extract chip parameters, and produce behavioral and circuit models for verification.
• Develop test plans and perform silicon bring-up, post-silicon validation, and lab debug.
• Optimize designs for power, performance, area, timing, yield, and leakage.
• Collaborate with architecture, layout, and verification teams; report design progress and resolve issues.
• Lead design reviews, mentor junior engineers, and set technical direction for projects.

Requirements

Must-have skills and experience:

• 8+ years experience in analog/mixed-signal circuit design for high-speed SerDes applications.
• Proven expertise in one or more of: PLL, CDR, CTLE, DFE, ADC, or transmitter design.
• Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).
• Solid analog design fundamentals: noise, jitter, matching, stability, and linearity.
• Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
• Proficiency with analog design and simulation tools (Cadence Virtuoso/ADE, HSPICE, or equivalent).
• Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
• Effective communication, documentation, and presentation skills; strong problem-solving and ability to deliver under tight schedules.

Nice-to-have:

• Deep expertise in transmitter/receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.
• Familiarity with next-generation standards (PCIe 6.0+, 800G/1.6T Ethernet, JESD).
• Behavioral modeling (Verilog-A), MATLAB analysis, and automation scripting (Python, Tcl, Perl).
• Signal integrity, channel modeling, and system-level link performance experience.
• Proven ability to mentor junior engineers and guide layout implementation; demonstrated cross-functional leadership.

Education Requirements

Minimum: Master’s degree in Electrical Engineering, Electronics Engineering, or a related field. Preferred: Ph.D. in Electrical/Electronics Engineering or a related discipline. (Degrees and fields cited in the posting.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.