Principal Analog Circuit Design Engineer - SerDes

Job Title

Principal Analog Circuit Design Engineer - SerDes

Role Summary

Design and deliver high-speed analog and mixed-signal SerDes IP in advanced FinFET process nodes. Work within a central engineering organization to define technical direction, drive execution across design, layout and bring-up, and mentor other engineers.

As a principal engineer, provide domain expertise for transmitter/receiver architectures and validation, and influence cross-functional design decisions to meet power, performance, area, timing, and yield targets.

Experience Level

Senior-level (Principal). Posting specifies a minimum of 8+ years of relevant analog/mixed-signal SerDes design experience.

Responsibilities

Deliver and validate analog/mixed-signal SerDes circuits from specification through silicon:

• Architect, design and simulate analog circuits (PLL, CDR, CTLE, DFE, ADC, TX/RX) in advanced process nodes.
• Create floorplans, extract chip parameters, and produce behavioral and circuit-level models for system integration.
• Develop test plans and perform pre- and post-silicon validation, lab debug and silicon bring-up.
• Optimize designs for power, performance, area, timing and yield; reduce leakage and improve robustness.
• Collaborate with architecture, layout, verification and system teams to resolve design issues and ensure electrical/functional goals.
• Lead design reviews, make architectural trade-offs, and drive decisions across teams.
• Mentor and develop other technical leaders and contribute to team growth and technical strategy.

Requirements

Key must-have skills and experience for successful performance in this role. Education requirements are listed separately below.

• Must-have: 8+ years of analog/mixed-signal circuit design experience for high-speed SerDes applications.
• Technical expertise in one or more: PLL, CDR, CTLE, DFE, ADC, or transmitter design.
• Working knowledge of high-speed standards such as PCIe Gen5/Gen6 and Ethernet (100G/400G/800G).
• Strong analog fundamentals: noise, jitter, matching, stability and linearity.
• Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
• Proficiency with analog design/simulation tools (Cadence Virtuoso/ADE, HSPICE or equivalent).
• Experience in silicon bring-up, post-silicon validation and lab debug of analog circuits.
• Clear communication, documentation and presentation skills; ability to deliver under tight schedules.
• Nice-to-have: experience with behavioral modeling (Verilog-A), MATLAB analysis, automation scripting (Python/Tcl/Perl), and deep system-level link/channel analysis (signal integrity, channel modeling).
• Familiarity with next-generation standards (PCIe 6.0+, 800G/1.6T Ethernet, JESD) and demonstrated leadership mentoring junior engineers is preferred.

Education Requirements

Master's degree in Electrical Engineering, Electronics Engineering, or a related field is required. Ph.D. in Electrical/Electronics Engineering or related field is preferred. (Degrees and fields explicitly specified in the posting.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.