Principal AMS Verification Engineer

Job Title

Principal AMS Verification Engineer

Role Summary

Responsible for owning and executing end-to-end verification strategy for high-speed mixed-signal SerDes IPs. Works closely with analog, digital, architecture, and validation teams and provides technical leadership across projects.

Supports silicon bring-up, post-silicon debug, and correlation activities while mentoring junior verification engineers.

Experience Level

Senior — Principal-level role. Requires 10+ years of experience in AMS verification and SerDes IP verification.

Responsibilities

Primary responsibilities include defining verification strategy, building verification environments, and leading complex mixed-signal verification efforts.

• Define and drive AMS verification strategy for high-speed SerDes IPs from concept to signoff.
• Architect and develop UVM and UVM-AMS based verification environments.
• Verify mixed-signal SerDes subsystems at IP, subsystem, and SoC levels, including multi-lane and multi-protocol operation.
• Develop, integrate, and validate RNM, Verilog-AMS, and behavioral models.
• Lead verification of link training, initialization, adaptation, BIST, PRBS, loopback, error injection, and robustness scenarios.
• Analyze and debug mixed-signal issues involving timing, jitter, noise, and protocol behavior; perform corner, PVT, stress, and performance verification.
• Collaborate with analog design, digital RTL, architecture, and validation teams; contribute to silicon bring-up and post-silicon correlation.
• Mentor and provide technical guidance to junior verification engineers.

Requirements

Must-have technical skills and tools; nice-to-have items noted.

• Must-have: Strong hands-on experience with SystemVerilog, UVM, and UVM-AMS.
• Must-have: Expertise in Verilog-AMS, AMS RNM, and wreal modeling.
• Must-have: Experience with mixed-signal simulators such as Cadence Xcelium AMS, Synopsys VCS AMS, or Siemens Questa ADMS and strong mixed-signal debugging skills.
• Must-have: Deep understanding of SerDes architectures (TX/RX data paths, PLLs, CDRs, CTLE/DFE/FFE equalization, clocking, jitter tolerance, signal integrity).
• Must-have: Experience verifying USB and DisplayPort SerDes protocols; familiarity with PCIe, Ethernet, HDMI, MIPI, SATA is beneficial.
• Must-have: Experience with multi-lane, multi-rate, and multi-protocol SerDes IPs.
• Must-have: Proficiency in Python, Perl, or Tcl for automation of regression flows, result analysis, and reporting.
• Nice-to-have: MATLAB or Python system modeling, transistor-level correlation, and experience balancing accuracy versus simulation performance.

Education Requirements

Bachelor's or Master's degree in Electrical or Electronics Engineering or a related field. Master’s degree preferred for principal-level roles.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.