Power Management Design Engineer

Job Title

Power Management Design Engineer

Role Summary

Design and micro-architect power-management, reset, and clocking subsystems for RISC-V CPU and SoC IP. Work within an RTL design team to deliver configurable, high-performance, energy-efficient hardware IP from architecture through tapeout.

Collaborate with architecture, verification, physical implementation, and software teams to meet frequency, area, power, and functional requirements.

Experience Level

Mid-level (3+ years industry experience)

Responsibilities

Primary responsibilities include architecture, RTL design, verification support, and implementation collaboration for power/reset/clock solutions.

• Define power-management requirements with the architecture team.
• Architect and implement core clocking, reset, and power-management logic.
• Develop microarchitecture specifications and document designs for team use.
• Perform initial sandbox verification and support creation/execution of verification test plans with DV engineers.
• Collaborate with physical implementation to meet frequency, area, and power targets.
• Work with software to enable and optimize power-management features.

Requirements

Must-have technical skills and professional experience.

• 3+ years recent industry experience in CPU/SoC clocking, reset, and power-management logic design.
• Experience with high-performance, energy-efficient CPU and SoC designs and successful delivery from architecture through tapeout.
• Expertise in reset control, clock distribution, clock gating, clock boundary crossing strategies, and power-management unit (PMU) design.
• Knowledge of power state management, dynamic/static power reduction techniques (retention, sequencing), DVFS, and Di/dt mitigation.
• Familiarity with DFT, MBIST, debug and error handling in CPU designs; power-aware simulation.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Understanding of RTL quality checks such as linting, CDC, and RDC; hands-on experience with Spyglass is a plus.
• Experience with at least one object-oriented and/or functional programming language.
• Attention to detail and ability to work effectively in cross-functional engineering teams.

Nice-to-have:

• Experience with AMBA protocols (AXI, AHB, APB) and AMBA low-power interfaces (P-channel, Q-channel).
• Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware generators.
• Knowledge of RISC-V architecture and experience with Git/GitHub, Jira, Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.