Power Management Design Engineer

Job Title

Power Management Design Engineer

Role Summary

Design micro-architecture and RTL for power management, reset and clocking subsystems for RISC-V CPU and SoC IP. Work on highly configurable IP generators and collaborate with architecture, verification, physical implementation, and software teams to deliver production-quality hardware.

Experience Level

Mid-level — requires approximately 3+ years of relevant industry experience in CPU/SoC clocking, reset, and power-management logic design.

Responsibilities

Primary responsibilities include micro-architecture, RTL implementation, verification support, and cross-team integration to meet performance, area, and power goals.

• Define power-management, reset, and clocking requirements with architects and system teams.
• Architect, micro-architect, specify and implement core clocking, reset, and PMU solutions.
• Develop RTL and perform initial sandbox verification; collaborate with verification team on test plans and execution.
• Work with physical implementation teams to optimize timing, area, and power during place-and-route.
• Collaborate with software teams to enable and optimize power-management features and firmware interfaces.
• Document designs and share knowledge to support a collaborative engineering process.

Requirements

Must-have technical skills and experience.

• 3+ years of industry experience in CPU/SoC clocking, reset, and power-management logic design.
• Expertise in clock distribution, dynamic clocking, clock gating, and clock boundary crossing strategies.
• Experience with PMU design, power-state definition/management, retention, and power-up/down sequencing.
• Knowledge of dynamic/static power reduction techniques, DVFS, and Di/dt mitigation strategies.
• Familiarity with DFT, MBIST, debug and error-handling practices for CPU designs.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Understanding of RTL quality checks (Lint, CDC, RDC); hands-on Spyglass experience is a plus.
• Background in CPU or SoC development through architecture and tapeout.
• Experience with at least one object-oriented or functional programming language.
• Attention to detail and ability to work effectively on cross-functional teams.

Nice-to-have:

• Experience with AMBA protocols (AXI, AHB, APB) and AMBA Low Power Protocol interfaces.
• Experience with Scala/Chisel, Bluespec, or other hardware DSLs.
• Knowledge of RISC-V architecture and common development tooling (Git/GitHub, Jira, Confluence).

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.