Power Integrity Co-Design Engineer

Job Title

Power Integrity Co-Design Engineer

Role Summary

The Power Integrity Co-Design Engineer architects and delivers di/dt and voltage-noise mitigation across silicon, package, board, and platform. This role translates product noise targets into ship-ready specs, leads Sim-to-Si correlation, and coordinates codesign tradeoffs across architecture, silicon, and platform teams.

Experience Level

Mid-level — typically requires approximately 4+ years of relevant experience in silicon power integrity, voltage noise, or PDN.

Responsibilities

Key responsibilities include defining noise targets, architecting mitigation across the stack, and driving cross-functional closure.

• Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
• Architect voltage-noise mitigation across silicon, package, board, and platform; lead codesign tradeoffs among these domains.
• Co-design noise features with Speed/Power/Reliability, circuit, power-architecture, ASIC, and platform teams.
• Build and lead Sim-to-Si correlation methodology for voltage noise.
• Model and prototype next-generation noise features (transient sensing, droop response, mitigation IP).
• Lead resolution of show-stopper noise issues during bring-up and characterization.
• Drive architecture-level tradeoffs across voltage/frequency, power, noise, reliability, and thermal boundaries.

Requirements

Must-have technical skills, practical bench and simulation experience, and ability to drive cross-functional decisions.

• 4+ years of practical experience in silicon power integrity, voltage noise, or PDN design and analysis.
• Deep expertise in at least one area: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, or decap budgeting.
• Hands-on silicon experience: bring-up, characterization, correlation; comfortable on a bench with scopes, probes, and DAQ and using simulators.
• Strong Sim-to-Si correlation instincts and the independence to challenge results when appropriate.
• Proven application of AI/ML techniques to accelerate power-integrity tasks (noise modeling, transient prediction, Sim-to-Si analysis), with sound judgment about model limits.
• Ability to drive multi-functional decisions, write and own specs, and lead sign-offs across partners.
• Nice-to-have: patents or publications in power integrity/PDN; experience with GPU/CPU/AI accelerator silicon at advanced nodes; validated ML/AI applications for noise modeling or transient prediction.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.