Power Architect – AI SOC

Job Title

Power Architect – AI SOC

Role Summary

Lead power, performance, and area (PPA) delivery for a next-generation AI SoC. Work across architecture, RTL, and physical design teams to define and implement power and thermal management strategies that meet strict energy-efficiency targets for AI inference and training workloads.

The role is cross-functional and technical: you will influence microarchitecture, guide RTL and floorplanning decisions, develop PD recipes, and integrate custom EDA/automation solutions to minimize power and meet timing and area goals.

Experience Level

Senior - requires extensive industry experience. The role requests 12+ years of semiconductor experience focused on SoC architecture, low-power RTL design, and physical design implementation.

Responsibilities

Primary responsibilities include end-to-end PPA ownership, tool and flow development, and cross-team coordination.

• Define and drive SoC-level power and thermal management architecture, including multi-voltage domains and power sequencing.
• Influence microarchitecture, memory hierarchy, and dataflow choices to minimize dynamic and leakage power for AI workloads.
• Review and guide RTL to ensure alignment with power, timing, and floorplan constraints.
• Collaborate with Physical Design teams on floorplanning, area constraints, and multi-voltage domain implementation.
• Develop and tune Physical Design (synthesis, placement, CTS, routing) recipes to meet PPA targets.
• Lead PPA analysis, trade-off studies, and root-cause investigations across architecture, RTL, and PD teams.
• Partner with EDA vendors and internal teams to adopt and customize advanced power-analysis tools and flows.
• Build custom scripts, automation, and workflows to extend EDA capabilities and optimize power results.

Requirements

Must-have technical skills and proven outcomes.

• 12+ years of semiconductor industry experience with deep focus on SoC architecture, low-power RTL, and PD implementation.
• Proven track record delivering complex, high-performance silicon (AI accelerators, GPUs, or advanced SoCs) under strict PPA constraints.
• Hands-on experience with power intent methodologies and formats (UPF/CPF) and with industry power-estimation/analysis tools.
• Practical experience with advanced PD flows: synthesis, placement, clock-tree synthesis, and routing; ability to develop PD recipes.
• Strong scripting and automation skills (Python, Tcl, Perl) for EDA flow customization and PPA data analysis.
• Experience partnering with EDA vendors and developing custom tools or scripts where standard flows are insufficient.
• Effective cross-functional communication and leadership to resolve PPA trade-offs across teams.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. (Degree-level specified in original posting.)

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.