PLL Design/Integration Staff Engineer — Adaptive Computing Group

Job Title

PLL Design/Integration Staff Engineer — Adaptive Computing Group

Role Summary

Lead design, integration, and characterization of Phase-Locked Loops (PLLs) and related analog/mixed-signal IP for FPGA and Adaptive SoC products across advanced process nodes. Work with architecture, programmable fabric, integration, and software teams to deliver clocking solutions from IP through system-level validation and silicon bring-up.

Experience Level

Senior — Staff-level engineer. Specific years of experience not specified; role expects advanced technical and leadership experience in analog/mixed-signal IC and PLL design.

Responsibilities

Lead and execute PLL and clocking IP integration from architecture to silicon validation.

• Architect and integrate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, loop filters) and associated IP (LDOs, phase interpolators) into FPGA products.
• Integrate and optimize PLL topologies (integer-N, fractional-N, ADPLL) to meet power, area, jitter, and frequency requirements at product level.
• Address advanced-node challenges such as self-heating, electromigration, VCO linearization, and device-level noise for product jitter optimization.
• Verify and supervise PD/layout outputs to ensure proper floor-planning, matching, and parasitic minimization.
• Lead silicon bring-up and conduct lab performance characterization using modern test equipment.
• Perform system-level simulations and validation of PLL IP in FPGA environments using Vivado or equivalent flows.

Requirements

Core technical requirements and preferred skills.

• Proven experience in analog/mixed-signal IC design and PLL IP integration into SoC/FPGA products.
• Practical knowledge of silicon processes, packaging technologies, device physics, and reliability issues affecting analog performance.
• Hands-on silicon bring-up and lab characterization experience.
• Experience collaborating with architecture, digital design, verification, and software teams; strong communication and problem-solving skills.
• This role is not eligible for visa sponsorship.

Nice-to-have:

• Experience designing fractional-N PLLs, all-digital PLLs (ADPLL), or sub-sampling PLLs.
• Familiarity with LDOs, bias generators, operational amplifiers, and high-speed dividers.
• Background in digital design, digital verification, and SystemVerilog modeling; knowledge of clock synthesis/recovery techniques (DLLs, CDRs).

Education Requirements

Preferred: MS in Electrical & Electronics Engineering. Acceptable alternative: Bachelor’s degree in electrical/electronics engineering or a related technical field with several years of relevant industry experience. Equivalent practical experience in IC design and PLL engineering is acceptable.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.