Place and Route Design Automation Engineer

Job Title

Place and Route Design Automation Engineer

Role Summary

Join the Design Methodology and Automation team to develop and support automated place-and-route (P&R) tools, flows, and methodologies for next-generation FPGA silicon. The role requires collaboration with physical design, CAD, RTL, synthesis, and cross-functional engineering teams to improve quality of results, runtime, and flow robustness.

Experience Level

Mid-level — typically requires 3+ years of industry experience in semiconductor design or design automation and hands-on P&R or physical design experience.

Responsibilities

Primary responsibilities focus on developing, maintaining, and supporting P&R automation and methodologies for FPGA design.

• Develop and maintain P&R tools, flows, and automation infrastructure for FPGA silicon development.
• Contribute new methodologies and tool enhancements for next-generation P&R flows.
• Debug flow and tool issues and provide end-user support and best-practice guidance.
• Implement and improve scripts and automation utilities to increase usability, efficiency, and scalability.
• Improve P&R quality of results: timing, power, congestion, density, and design closure.
• Evaluate and test new P&R tool capabilities and methodologies; identify and resolve bottlenecks.
• Collaborate with multi-geo, cross-functional teams to ensure robust end-to-end flow support.
• Document methodologies, flow updates, and usage guidelines.

Requirements

Must-have technical skills and hands-on experience for successful performance in this role.

• 3+ years hands-on experience in Place & Route, physical design, or design automation within FPGA or ASIC environments.
• 3+ years using industry-standard P&R tools (e.g., Synopsys, Cadence) in production design environments.
• Strong scripting and automation skills: Tcl, Perl, and Python.
• Experience working in Unix/Linux development environments.
• Applied knowledge of physical design fundamentals: floorplanning, placement, clocking, routing, and static timing analysis.
• Experience debugging and resolving tool, flow, or design issues in collaborative engineering settings.
• Proven ability to work with cross-functional and multi-geo engineering teams to support design execution.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting specifies a Bachelor's plus 3+ years of industry experience in semiconductor design or design automation.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.