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Physical Verification Engineer (Lead/Staff/Sr Staff) - Custom Silicon Group

Qualcomm
October 2, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Physical Design Jobs, Level - Senior

Job Title

Physical Verification Engineer (Lead/Staff/Sr Staff) - Custom Silicon Group

Role Summary

Lead physical verification sign-off and convergence for advanced-node ASICs within the Custom Silicon Group. Work with physical design, custom layout, and foundry teams to ensure designs meet manufacturing and reliability criteria through DRC/LVS/ESD/PERC/ERC and related checks.

Contribute to methodology, automation, and flow improvements to achieve tape-out quality and productivity targets.

Experience Level

Senior (Lead/Staff/Sr Staff). Typical experience range 5–15 years; specific minimum varies by degree (see Education Requirements).

Responsibilities

Key responsibilities include sign-off ownership, cross-team collaboration, and technical leadership to resolve manufacturing and verification issues.

  • Drive physical verification sign-off activities: DRC, LVS, Antenna, ERC, PERC, ESD and related checks for advanced nodes.
  • Collaborate with Physical Design, Custom Layout, and Foundry teams to achieve clean sign-off and physical convergence.
  • Debug and resolve verification violations and drive closure to tape-out.
  • Support methodology development, automation, and flow enhancements to improve sign-off quality and productivity.
  • Participate in floorplanning, power planning, and PDN reviews to ensure robust physical implementation.

Requirements

Must-have:

  • Proven experience with physical verification sign-off flows and sign-off tools.
  • Familiarity with SVRF rule decks and sign-off tools such as Calibre and ICV.
  • Hands-on experience with implementation tools (Innovus, ICC2, Fusion Compiler) or equivalents.
  • Strong understanding of PDK concepts, Tech LEF, design rules, and foundry PDKs.
  • Experience on advanced technology nodes (e.g., 2nm, 3nm, 5nm, 7nm, 10nm).
  • Excellent debugging and problem-solving skills in sign-off environments.

Nice-to-have / Preferred:

  • Experience in floorplanning, power planning, and PDN design.
  • Team leadership or people management experience.
  • Scripting/automation skills (TCL, Perl, or other scripting languages).
  • Exposure to custom IC design flows, mixed-signal, or full-chip convergence efforts.
  • Familiarity with ESD reliability analysis and advanced PERC methodologies.

Education Requirements

Minimum qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of relevant hardware engineering experience; OR Master's degree in those fields with 5+ years; OR PhD in those fields with 4+ years. "Related field" acceptable per posting. (Experience ranges summarized separately in Experience Level.)


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-10-01