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Physical Verification Engineer

Salience Labs
November 5, 2026
Full-time
On-site
Oxford, ENG, United Kingdom
Physical Design Jobs, Level - Mid-Career

Job Title

Physical Verification Engineer

Role Summary

Drive DRC/LVS signoff for integrated circuit and photonic integrated circuit (PIC) layouts. Work with design, layout, and CAD teams to run, debug, and maintain verification flows against foundry PDKs to ensure tapeout readiness.

Experience Level

Mid-level - requires 3+ years of hands-on physical verification experience in IC design.

Responsibilities

Deliver and maintain physical verification flows and support layout signoff.

  • Run and debug physical verification (DRC, LVS, extraction) for IC and PIC layouts.
  • Investigate LVS/DRC discrepancies: port mismatches, hierarchy mismatches, device recognition issues.
  • Read, manipulate, and QA GDS/OASIS layout data.
  • Maintain and extend verification runsets and rule decks.
  • Develop Python/Tcl/shell tools to automate verification and triage error reports.
  • Manage verification libraries and runsets under version control with controlled releases.
  • Handle third-party and foundry IP per licensing terms.
  • Collaborate with design, layout, and CAD teams to close verification issues before tapeout.
  • Document known issues, workarounds, and runset changes.

Requirements

Must-have technical skills and practical experience.

  • 3+ years of hands-on physical verification experience in IC design.
  • Practical experience with Siemens Calibre and/or Synopsys ICV for DRC/LVS signoff.
  • Experience with custom/analog layout tools such as Cadence Virtuoso or Synopsys CustomCompiler.
  • Strong working knowledge of GDS/OASIS formats and LVS concepts.
  • Proficiency with Linux and scripting in Python, Tcl, or shell.
  • Experience managing rule decks, runsets, or libraries under version control (e.g., Git).
  • Ability to independently debug complex hierarchical netlist and layout issues.
  • Strong written communication for documenting root causes and fixes.

Nice-to-have:

  • Photonic IC verification experience.
  • Experience with Verilog/SystemVerilog netlists.
  • Exposure to foundry PDK qualification.
  • Experience building internal automation to scale verification.

Education Requirements

Not specified.


About the Company

Company: Salience Labs

Headquarters: Oxford, United Kingdom

Salience Labs develops integrated photonics technologies and solutions, focusing on experimental characterisation, device development and engineering for advanced optical and photonic systems. They work across photonic design, manufacturing and system testing, supporting R&D and product development.

Salience Labs logo

Date Posted: 2026-11-03