Physical Design Technical Lead

Job Title

Physical Design Technical Lead

Role Summary

The Physical Design Technical Lead owns end-to-end SOC and block-level physical implementation, from floorplanning and power intent through signoff. You will drive timing, power, and PPA closure while shaping ML/AI-assisted implementation flows and guiding cross-functional integration for advanced-node tapeouts.

Experience Level

Senior — requires extensive industry leadership; the role expects 15+ years of physical design or SoC backend experience with multiple advanced-node tapeouts and several years in a technical lead capacity.

Responsibilities

Lead physical implementation and flow innovation across large SOC projects, ensure signoff-quality results, and mentor a small team of engineers.

• Own floorplan architecture and power-domain partitioning for large multi-million-instance SOCs.
• Drive block and full-chip implementation through synthesis, place-and-route, CTS, ECO, and final signoff.
• Ensure timing, power, and area convergence across concurrent tapeouts; perform critical-path analysis and timing-driven ECOs.
• Deliver full signoff closure: MMMC STA, IR drop and EM analysis, DRC/LVS, antenna and other signoff checks.
• Define and enforce physical design guidelines, SDC/UPF constraint authoring, and methodology standards.
• Champion integration and productization of ML/AI optimization engines in production PnR flows and maintain feedback loops for model training.
• Collaborate with RTL, DFT, packaging, analog, CAD, and automation teams to resolve integration and implementability issues.
• Mentor and technically guide a team (typical span: 3–8 engineers); lead design and closure reviews and documentation.

Requirements

Must-have technical skills and proven delivery experience on advanced-node designs; preferred items listed separately.

• 15+ years of progressive industry experience in physical design, physical implementation, or SoC backend development.
• 4+ years in a technical lead, senior lead, or principal-level physical design role with ownership of complex deliveries.
• 3+ successful tapeouts with direct hands-on physical design ownership at advanced nodes (7nm or below).
• 5+ years of SoC-level floorplanning, top-level integration, and full-chip implementation experience.
• Hands-on experience with Fusion Compiler and/or Cadence Innovus; broad exposure to industry signoff suites.
• Extensive STA and timing-closure experience (MMMC analysis, SI/crosstalk, path-based analysis) and signoff flows (PrimeTime or equivalent).
• Power integrity and signoff experience (RedHawk, Voltus, or equivalent) and multi-voltage/low-power methodologies (UPF/CPF, MTCMOS, retention/isolation).
• Physical verification and signoff experience (Calibre DRC/LVS, PVS or equivalent) and strong scripting/automation skills (Tcl required; Python/Perl preferred).
• Practical experience using or evaluating ML/AI-driven physical design tools and applying model outputs to implementation decisions; familiarity with Python-based data pipelines for design metrics.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related discipline is specified. The posting pairs this degree expectation with the requirement for extensive industry experience (15+ years). No alternative "equivalent experience" language was provided.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.