Physical Design Staff Engineer
QualcommJob Title
Physical Design Staff Engineer
Role Summary
Senior physical design engineer responsible for end-to-end ASIC/SoC physical implementation and static timing analysis (STA) in the CPU domain. The role focuses on floorplanning, timing closure, power and IR-drop analysis, physical verification, ECO execution, and design-for-signoff optimization.
Works within Qualcomm's Hardware Engineering organization and collaborates with RTL, synthesis, verification, and ECO teams to deliver PPA and timing signoff on advanced process nodes.
Experience Level
Senior level. The posting expects experienced candidates, with the role specifically targeting engineers with approximately 8+ years of physical design / STA experience in the CPU domain. See Education Requirements for formal degree/experience combinations.
Responsibilities
Primary responsibilities include implementing and closing physical design and timing for CPU blocks, driving PPA improvements, and managing signoff across corners.
- Lead physical implementation from floorplan through place-and-route to timing signoff.
- Perform STA and timing closure across large designs and multiple corners.
- Prepare and apply complex ECOs for timing convergence using Tweaker / Tempus / physical PT ECOs or equivalent flows.
- Analyze and mitigate IR drop and physical verification issues; coordinate with power and layout teams.
- Optimize power, performance, and area (PPA) and apply low-power implementation techniques.
- Create and maintain automation/scripting to support implementation and signoff flows (Perl, TCL).
- Collaborate with cross-functional teams to push PPA targets and enable successful tapeout.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- Extensive physical design and STA experience in the CPU domain (targeting ~8+ years).
- Hands-on experience with industry implementation and signoff tools (examples listed in preferred: Genus, Innovus, Fusion Compiler, PT, Tempus, Voltus, RedHawk).
- Proven experience from floorplan to timing signoff, including handling ECOs across many corners.
- Strong timing fundamentals and experience with timing closure methodologies.
- Expertise in scripting and automation, specifically Perl and TCL.
- Ability to analyze and improve power (minimization) and PPA trade-offs.
- Strong problem-solving skills and willingness to drive aggressive PPA targets.
Nice-to-have:
- Experience with deep submicron process technology nodes.
- Knowledge of high-performance and low-power implementation techniques.
Education Requirements
Candidates typically hold a Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. The posting specifies degree-and-experience combinations: Bachelor's + 4+ years hardware-engineering experience; or Master's + 3+ years; or PhD + 2+ years.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
