Physical Design Staff Engineer

Job Title

Physical Design Staff Engineer

Role Summary

Lead timing closure, signoff readiness, and PPA optimization for advanced-node customer designs. Develop and maintain physical design methodologies, automation, and data-driven flows used across block, subsystem, and chip-level implementations.

Your work will directly affect tapeout schedules and first-pass silicon success for customers at 3nm, 2nm and beyond.

Experience Level

Senior-level role - typically requires 5+ years of ASIC physical design or implementation experience.

Responsibilities

Key responsibilities include:

• Drive timing closure, signoff readiness, and PPA optimization across block, subsystem, and chip-level designs.
• Develop and enhance physical design methodologies and automation to improve quality, predictability, and efficiency.
• Perform static timing analysis, clock-tree synthesis, and ECO implementation using industry tools.
• Analyze design data and trends to identify bottlenecks and build flows that improve subsequent tapeouts.
• Collaborate with design, verification, and CAD teams to ensure successful silicon delivery.
• Contribute to AI/ML-driven design optimization and data-driven engineering initiatives.
• Troubleshoot complex physical design issues and deliver scalable technical solutions.

Requirements

Must-have technical skills and experience:

• 5+ years of hands-on ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs.
• Deep knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies.
• Proficiency with implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus.
• Strong scripting and automation skills (TCL, Python, Perl, Pandas) to build flows and analyze data.
• Proven ability to diagnose tool behavior, analyze timing reports, and implement lasting methodology changes.
• Excellent problem-solving and communication skills; comfortable coordinating across global teams.
• Nice-to-have: experience with advanced-node design at 7nm or below.
• Nice-to-have: exposure to machine learning or AI-assisted design optimization.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.