Physical Design Sr/Lead/Staff Engineer - Camera
QualcommJob Title
Physical Design Sr/Lead/Staff Engineer - Camera
Role Summary
Responsible for physical implementation of Camera subsystem IP, owning end-to-end physical design from netlist to GDSII and working to meet stringent power, performance, and area (PPA) targets.
The role partners with design and CAD teams, engages with external CAD vendors, and implements optimization and low-power techniques to achieve timing closure and signoff.
Experience Level
Senior-level (Sr/Lead/Staff). Posting indicates 3–15 years of Physical Design experience; minimums listed by degree: Bachelor's +4 years, Master's +3 years, PhD +2 years.
Responsibilities
Principal responsibilities include physical implementation, optimization, and cross-team collaboration for Camera PNR designs.
- Execute floorplanning, place-and-route (PNR), CTS, and STA signoff for Camera blocks.
- Own end-to-end physical implementation flows from netlist to GDSII, including post-route optimization and signoff.
- Develop and apply optimization techniques to meet PPA targets and reduce power consumption.
- Implement and validate low-power methods such as voltage islands and PDN design.
- Perform IR drop analysis, physical verification, and power integrity checks.
- Implement complex ECOs and timing convergence across multiple corners using vendor flows and in-house tools.
- Collaborate with block-level teams, CAD engineers, and external tool vendors to resolve implementation issues.
- Document implementation choices and deliverables to support signoff and handoff.
Requirements
Core technical skills and hands-on experience required for successful execution of Camera physical design.
- Proven expertise in physical design: floorplanning, PNR, CTS, STA closure, and post-route optimization.
- Hands-on experience with industry tools such as Fusion Compiler, Genus, Innovus, PrimeTime, Tempus, Voltus, and RedHawk.
- Experience implementing low-power methodologies, voltage islands, and PDN design.
- Strong focus on PPA optimization and power reduction techniques.
- Ability to implement complex ECOs and use timing tools for multi-corner convergence (e.g., Tweaker/Tempus/PrimeTime ECO flows).
- Proficiency in scripting (Perl, Python, TCL) to automate flows and analyses.
- Solid fundamentals in VLSI and Physical Design concepts; strong troubleshooting and debugging skills.
- Nice-to-have: experience in deep-submicron nodes and high-performance/low-power implementation techniques.
Education Requirements
Required: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field plus 4+ years of relevant hardware engineering experience; OR Master's degree in those fields plus 3+ years of relevant experience; OR PhD in those fields plus 2+ years of relevant experience. The posting lists degree-based experience minimums explicitly.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
