Physical Design - SOC Top Lead

Job Title

Physical Design - SOC Top Lead

Role Summary

Lead ownership of system-on-chip top-level physical design from block integration through timing, power, signal integrity, verification, and tapeout-ready GDS. Act as the single point of ownership coordinating block PD owners, DFT, package/IO, verification, and architecture to achieve full-chip convergence.

This is a hands-on technical leadership role at an early-stage hardware team focused on FinFET technologies and energy-efficient processor platforms.

Experience Level

Senior — expects extensive senior-level physical design experience (see Requirements). The role targets candidates with multiple full-chip tapeouts and proven SoC-level closure experience.

Responsibilities

Accountable for top-level physical implementation and cross-team convergence to achieve tapeout readiness.

• Full-chip integration: floorplanning, power planning, macro/hard-IP placement, and top-level block partitioning.
• Timing closure: full-chip STA across corners and modes, cross-boundary timing, and SDC ownership.
• Power: PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy.
• Physical verification: top-level DRC/LVS/antenna closure, seal ring integration, and ECO coordination.
• Signal integrity & noise: crosstalk, di/dt, and chip-level noise closure around high-speed IO and PLL/analog boundaries.
• Clock & reset architecture: top-level clock strategy and CTS coordination with block owners.
• DFT integration: chip-level scan stitching, MBIST/JTAG integration, and ATPG/test coverage coordination.
• Package/IO co-design: bump/ball map coordination, IO ring planning, and package-aware floorplanning.
• Tapeout readiness: own sign-off checklist for timing, power, physical, and reliability; final GDS handoff.
• Cross-team coordination and schedule-risk management between PD, DV, DFT, package engineering, and architecture.
• Technical leadership and mentoring: set methodology and flow standards for chip-top closure and mentor block-level PD engineers.

Requirements

Must-have skills, tools, and experience to perform the role; followed by relevant nice-to-have items.

• Must-have: 8–12+ years of physical design experience with at least 2–3 full tapeouts at the chip-top/SoC integration level.
• Must-have: Deep hands-on experience with advanced FinFET nodes.
• Must-have: Proven track record owning full-chip timing closure across multiple corners and modes.
• Must-have: Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent).
• Must-have: Experience with chip-level DFT integration (scan stitching, MBIST, JTAG).
• Must-have: Tool fluency: Innovus (or ICC2), Tempus/PrimeTime, RedHawk, Calibre.
• Must-have: Excellent scripting skills in TCL, shell, and Python.
• Must-have: Demonstrated ability to lead technically across multiple teams; comfortable with high ownership and ambiguity in a small, fast-moving team.
• Nice-to-have: Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map).
• Nice-to-have: Experience with non-standard architectures (dataflow, tiled, NoC-based) or integrating analog/mixed-signal macros at top level.
• Nice-to-have: Knowledge of computer architecture, circuit design, device physics, and deep sub-micron implications to PD.

Education Requirements

Master's degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years of industry experience.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.