Physical Design Manager

Job Title

Physical Design Manager

Role Summary

Lead hands-on physical design and timing-closure activities for processor and accelerator ASIC blocks within Marvell’s Custom Processor and ASIC Solutions organization. Combine technical ownership, execution, and first-line people leadership to deliver timing-closed silicon for AI, cloud compute, and networking applications.

This position is onsite in Westborough, MA. Relocation assistance is available for qualified candidates.

Expected base pay range (USD): 185,900 - 275,170 per annum.

Experience Level

Senior — Principal-level role. Typical experience expectations: 10–15 years with a Bachelor’s, or 5–10 years with an advanced degree, or equivalent professional experience.

Responsibilities

The manager will combine hands-on execution with team leadership and technical ownership.

• Serve as primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems.
• Perform hands-on physical design and timing analysis, including late-stage debug and convergence.
• Define and drive closure strategy and act as a technical escalation point.
• Lead and mentor a small team of PD engineers as a player-coach; provide prioritization and day-to-day execution guidance.
• Coordinate closely with STA, RTL, CAD, and Program teams to resolve complex issues.
• Support hiring, onboarding, and ramp-up of new team members while maintaining technical ownership.
• Communicate execution status, risks, and tradeoffs clearly to engineering leadership.

Requirements

Must-have technical and leadership capabilities.

• Principal-level physical design experience delivering timing-closed ASICs or complex SoCs.
• Extensive timing analysis and closure experience across multiple designs.
• Deep knowledge of advanced timing topics (SI, CDC, LVF, POCV) and related methodologies.
• Proficiency with PD and STA tools (e.g., Synopsys PrimeTime or equivalent), scripting, and UNIX/Linux environments.
• Strong written and verbal communication skills to articulate technical tradeoffs.
• Proven experience leading PD engineers in a hands-on, player-coach capacity and mentoring engineering talent.
• Ability to coordinate execution across cross-functional teams with clear ownership and accountability.

Nice-to-have:

• Experience owning full-chip or large-subsystem PD and timing closure.
• Timing methodology and flow development experience.
• Experience with multi-site or globally distributed teams and balancing FTE and contractor resources.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field (typical expectation: 10–15 years’ related experience); or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5–10 years’ related experience; or equivalent professional experience in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.