Physical Design Manager

Job Title

Physical Design Manager

Role Summary

Manage the physical design (PD) implementation of large switching chips, overseeing the RTL-to-GDSII flow and delivery of tape-outs that meet timing, area, and power targets. Lead a team of PD engineers within the Switch PD Group and coordinate cross-functionally with architecture, verification, backend and tape-out teams.

Experience Level

Senior — requires extensive hands-on physical design experience and several years in a managerial role; the posting specifies at least 10 years of physical design experience and several years as a manager.

Responsibilities

Primary responsibilities include technical leadership, delivery, and process ownership for complex PD projects.

• Lead implementation of large, high-complexity switching chips across all PD disciplines from RTL to GDSII.
• Ensure tape-outs meet schedule and target speed, area, and power metrics.
• Own timing closure, signoff readiness, and PD quality standards.
• Manage, mentor, and grow a team of physical design engineers.
• Coordinate design handoffs and integration with architecture, verification, backend and tape-out teams.
• Drive tooling, methodology, and process improvements for productivity and quality.

Requirements

Must-have technical and leadership qualifications. Education details are in the Education Requirements section below.

• Minimum 10 years of hands-on physical design experience.
• Several years of experience managing physical design engineers or teams.
• Proven experience with PD flows: place & route, timing closure, and signoff processes for large chips.
• Experience working on large, complex chip designs with strong emphasis on quality and tape-out delivery.
• Scripting and automation experience (for example: Tcl, Python, Perl) to support PD flows.
• Strong leadership, project management, and cross-functional communication skills.
• Ability to work in a deadline-driven tape-out environment and drive team execution.
• May require eligibility to access export-controlled technology; candidates may be subject to export license review prior to employment.
• Nice to have: experience with switching/network chips, advanced process nodes, or PD tooling/EDA tool expertise.

Education Requirements

BSc or MSc in Electrical Engineering or Computer Science.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.