Physical Design Lead (High‑Speed IPs) — Principal Member of Technical Staff

Job Title

Physical Design Lead (High‑Speed IPs) — Principal Member of Technical Staff

Role Summary

Lead the physical implementation of high‑speed interface IPs (DDR/LPDDR/GDDR, PCIe, SerDes and mixed‑signal PHYs) across client, server, and graphics products. Drive architecture/implementation co‑optimization to meet aggressive power, performance, area, and schedule targets on advanced process nodes.

Work as a technical leader across architects, circuit designers, RTL, package, SI/PI, SoC, CAD and EDA vendors; provide technical direction, mentor engineers, and improve implementation methodologies and automation.

Experience Level

Senior / Principal level. The posting requests extensive industry experience; 15+ years of relevant physical design experience is preferred.

Responsibilities

Accountable for end‑to‑end physical implementation and technical leadership for complex high‑speed IP programs.

• Lead physical design for high‑speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes and related subsystems.
• Drive floorplanning, power planning, placement, clock architecture, CTS, timing closure, signal integrity closure, physical verification, and tapeout signoff.
• Optimize PHY architecture with architects and circuit designers to meet PPA and implementation constraints.
• Resolve complex implementation, silicon correlation, and post‑silicon issues.
• Develop and deploy implementation methodologies, automation, and AI‑assisted flows to improve quality and productivity.
• Collaborate with cross‑functional teams (Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, EDA vendors).
• Provide technical leadership across multiple projects and locations; mentor SMTS/MTS engineers and grow team capability.

Requirements

Key technical and leadership requirements. MUST include domain expertise and practical delivery experience.

• Must have: Deep expertise in timing closure, clock architecture/CTS, physical implementation, power optimization, and signal integrity.
• Must have: Proven experience delivering multiple successful tape‑outs on advanced process nodes and closing timing at aggressive frequencies.
• Must have: Extensive experience with high‑speed interface IPs (DDR4/DDR5/LPDDR5/LPDDR6, GDDR, PCIe, mixed‑signal PHYs).
• Must have: Strong experience with industry‑standard implementation and signoff EDA tools (Cadence, Synopsys) and signoff flows.
• Must have: Practical skills in SI/PI analysis, multi‑voltage methodologies, package interactions and RDL/ESD considerations.
• Must have: Programming/scripting for automation (Tcl, Python) and experience driving methodology/automation initiatives.
• Must have: Demonstrated technical leadership across cross‑functional teams and geographies; mentoring experience.
• Nice to have: Experience with AI‑assisted design flows and advanced node (N3/N4/N5 or equivalent) implementations.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, VLSI Design, or a related field. PhD preferred but not required.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.