Physical Design Lead (High-Speed IPs)

Job Title

Physical Design Lead (High-Speed IPs)

Role Summary

AMD is seeking a Principal Member of Technical Staff to lead physical implementation of high-speed interface IPs (DDR, LPDDR, GDDR, PCIe, SerDes and mixed‑signal PHYs) for client, server, and graphics products. The role owns end-to-end implementation, PPA co-optimization, and cross-functional coordination with architecture, RTL, AMS, package, SI/PI, SoC, and EDA teams.

Expect to drive methodology improvements, automation and mentor engineers while meeting aggressive frequency, power and schedule targets on advanced process nodes.

Experience Level

Senior — Principal/Lead role. Preferred 15+ years of industry experience in physical design for advanced semiconductor products.

Responsibilities

Lead and own physical design activities for high-speed IPs across the full implementation flow. Key responsibilities include:

• Lead physical implementation of DDR/LPDDR/GDDR PHYs, PCIe, SerDes and related subsystems.
• Floorplanning, power planning, placement, clock architecture, CTS, timing closure, signal integrity closure, and physical verification through tapeout signoff.
• Drive high-frequency timing closure and complex clock distribution designs.
• Co-optimize PHY architecture with architects and circuit designers for PPA and implementation efficiency.
• Develop and deploy implementation methodologies, automation and AI-assisted flows to improve quality and scalability.
• Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors.
• Debug and resolve complex implementation, silicon correlation, and post‑silicon issues.
• Provide technical leadership across multiple projects and mentor SMTS/MTS engineers.

Requirements

Must-have technical skills and experience:

• Extensive experience delivering multiple tape-outs on advanced process nodes (N3/N4/N5 or equivalent).
• Deep expertise in timing closure, STA, clock architecture and CTS, and physical implementation.
• Strong experience in power optimization, multi‑voltage methodologies, and IR/EM analysis.
• Proven skills in signal integrity and power integrity analysis and closure.
• Experience with high-speed interface IPs (DDR4/DDR5/LPDDR5/LPDDR6, GDDR, PCIe, mixed‑signal PHYs).
• Expertise with Cadence and Synopsys implementation and signoff flows.
• Scripting experience (Tcl, Python) and experience driving methodology development and automation.
• Demonstrated technical leadership and ability to influence cross-functional teams.

Nice-to-have:

• Experience with RDL, package interactions, ESD considerations and analog integration challenges.
• Familiarity with AI-assisted design flows and advanced automation techniques.
• PhD in a relevant field (preferred).

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, VLSI Design, or a related field. PhD preferred but not required.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.