Physical Design Lead - Execution

Job Title

Physical Design Lead - Execution

Role Summary

Senior individual-contributor responsible for owning day-to-day physical design execution from block floorplan through full-chip tapeout. Acts as the execution owner coordinating multiple block teams, ensuring schedule and quality, and representing execution to senior customers.

Experience Level

Senior (Principal / Sr. Principal). Principal: approximately 12+ years of physical design experience; Sr. Principal: approximately 15+ years, with multiple full-chip tapeouts and direct execution ownership.

Responsibilities

Accountable for end-to-end physical design execution and cross-team coordination. Key responsibilities include:

• Drive day-to-day physical design execution and delivery across blocks and full-chip integration (floorplan through tapeout).
• Own the schedule and quality bar; surface risks early and drive mitigation to meet milestones.
• Coordinate conflicts and dependencies across block teams to keep full-chip closure on track.
• Expand scope toward full-chip implementation ownership and build organizational judgment.
• Engage senior customer technical stakeholders and represent execution credibly in reviews.
• Serve as escalation point for execution blockers and lead pragmatic, fast resolutions under schedule pressure.
• Partner with methodology and CAD teams to align execution practices with signoff standards and quality gates.
• Mentor engineers on execution best practices, prioritization, and schedule management.

Requirements

Must-have technical skills and experience:

• Direct execution ownership for block and full-chip delivery, with accountability for schedule and quality outcomes.
• Hands-on expertise across the physical design flow: floorplanning, placement, clock-tree synthesis, routing, and timing/power closure, including signoff interactions.
• Production physical design execution at advanced nodes (e.g. 7nm / 5nm / 3nm or comparable), familiar with parasitic and reliability challenges.
• Proficiency with industry implementation and signoff tools (examples: Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre); experience with every tool is not required.
• Working command of signoff flows that gate tapeout: STA, EMIR, physical verification, formal equivalence, and low-power verification.
• Scripting and automation proficiency (Python, Tcl, Perl, or shell) sufficient to build and debug execution tooling.
• Experience driving execution on high-complexity designs with concurrent block teams across multiple sites and resolving conflicting priorities.
• Strong communication and customer-facing skills; able to present to senior stakeholders and manage critical-path recovery.

Preferred:

• Experience serving as an implementation lead or execution owner for a full chip or major subsystem.
• Direct experience representing physical design execution in customer-facing technical reviews.
• Familiarity with PD signoff methodology and experience mentoring or informally leading execution teams.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field. Role expects Principal-level candidates to have ~12+ years and Sr. Principal ~15+ years of physical design experience, including a minimum of four full-chip tapeouts at advanced nodes with direct execution ownership.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.